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@icgrp Penn Implementation of Computation Group

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    23 repositories

    • prflow_REFINE

      Public
      REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs (FPGA 2024)
      C
      •0•5•0•0•Updated Nov 11, 2024Nov 11, 2024

    • ese532_handouts

      Public
      Course handouts for ESE532 at UPenn
      fpgahlsxilinxsystem-on-chip
      Shell
      •4•3•0•0•Updated Oct 23, 2024Oct 23, 2024

    • ese532_code

      Public
      C++
      •
      MIT License
      •16•9•0•0•Updated Oct 22, 2024Oct 22, 2024

    • prflow_nested_dfx

      Public
      Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)
      C
      •0•12•0•0•Updated Mar 21, 2024Mar 21, 2024

    • old_systolic_placer

      Public
      Updated systolic placer
      C++
      •
      Other
      •395•0•0•0•Updated Aug 7, 2023Aug 7, 2023

    • asym_bft

      Public
      Asymmetry in Butterfly Fat Tree FPGA NoC (FPT 2023)
      Verilog
      •0•1•0•0•Updated Jul 13, 2023Jul 13, 2023

    • hipr

      Public
      Verilog
      •
      MIT License
      •2•14•0•0•Updated Feb 3, 2023Feb 3, 2023

    • rosetta_vitis

      Public
      Verilog
      •
      BSD 3-Clause "New" or "Revised" License
      •1•6•0•0•Updated Nov 4, 2022Nov 4, 2022

    • pld2022

      Public
      C
      •
      MIT License
      •0•14•1•0•Updated Oct 25, 2022Oct 25, 2022

    • doblink

      Public
      C
      •
      MIT License
      •1•2•0•0•Updated Jul 29, 2022Jul 29, 2022

    • symbiflow-arch-defs

      Public
      FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
      Jupyter Notebook
      •
      ISC License
      •113•1•0•0•Updated Dec 2, 2021Dec 2, 2021

    • bert

      Public
      Bitstream Embedded RAM Transfusion
      C
      •
      ISC License
      •4•9•1•0•Updated Aug 4, 2021Aug 4, 2021

    • vtr-verilog-to-routing

      Public
      Verilog to Routing -- Open Source CAD Flow for FPGA Research
      C++
      •
      Other
      •395•0•0•0•Updated Jul 14, 2021Jul 14, 2021

    • nestedDFX

      Public
      This is repo to show how to use nested DFX on ZCU102 board
      Tcl
      •1•2•0•0•Updated Jun 10, 2021Jun 10, 2021

    • hydra

      Public
      Hydra is a framework for elegantly configuring complex applications
      Python
      •
      MIT License
      •639•0•0•0•Updated May 27, 2021May 27, 2021

    • pythondata-cpu-vexriscv-stream

      Public
      Python module containing verilog files for vexriscv cpu (for use with LiteX).
      Verilog
      •
      MIT License
      •39•0•0•0•Updated May 3, 2021May 3, 2021

    • estream4fccm2021

      Public
      VHDL
      •
      MIT License
      •0•2•0•0•Updated Apr 20, 2021Apr 20, 2021

    • fpga-tool-perf

      Public
      FPGA tool performance profiling
      Python
      •
      ISC License
      •30•0•0•0•Updated Apr 13, 2021Apr 13, 2021

    • huffmanVivadoProject

      Public
      huffmanVivadoProject submodule for bert
      VHDL
      •0•0•0•0•Updated Apr 9, 2021Apr 9, 2021

    • slurm-gcp

      Public
      Slurm on Google Cloud Platform
      Python
      •
      Apache License 2.0
      •120•0•0•0•Updated Mar 28, 2021Mar 28, 2021

    • edalize

      Public
      An abstraction library for interfacing EDA tools
      Python
      •
      BSD 2-Clause "Simplified" License
      •193•0•0•0•Updated Feb 10, 2021Feb 10, 2021

    • prjxray

      Public
      Documenting the Xilinx 7-series bit-stream format.
      Python
      •
      ISC License
      •152•0•0•0•Updated Dec 4, 2020Dec 4, 2020

    • rosetta

      Public
      Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
      C++
      •
      BSD 3-Clause "New" or "Revised" License
      •38•0•0•0•Updated Mar 17, 2020Mar 17, 2020