Experiment with simd_masked_load to read beyond without undefined behavior #98
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RalfJung
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Nov 6, 2024
src/gxhash/platform/arm.rs
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| let indices = vld1q_s8([0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15].as_ptr()); | ||
| let mask = vreinterpretq_s8_u8(vcgtq_s8(vdupq_n_s8(len as i8), indices)); | ||
| std::intrinsics::simd::simd_masked_load(mask, data as *const i8, vdupq_n_s8(len as i8)) |
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So do I understand correctly that it would be valid for LLVM to basically emit the same assembly as before, but somehow it doesn't?
I'm not a codegen expert so I have no idea whether this is just hard for LLVM to do or something they could reasonably fix. Maybe it'd be worth making an LLVM bugreport about this? (We can try to find some people that could help nail down the core issue here, if you are interested.)
# Conflicts: # benches/throughput/aarch64.svg # benches/throughput/x86_64-hybrid.svg # benches/throughput/x86_64.svg
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