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[nrf fromlist] soc: nordic: dmm: Fix DMM_REG_ALIGN_SIZE macro when CO… #2210

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Nov 1, 2024
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[nrf fromlist] soc: nordic: dmm: Fix DMM_REG_ALIGN_SIZE macro when CO… #2210

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18 changes: 13 additions & 5 deletions soc/nordic/common/dmm.h
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Original file line number Diff line number Diff line change
Expand Up @@ -23,19 +23,27 @@

/** @cond INTERNAL_HIDDEN */

#ifdef CONFIG_DCACHE

/* Determine if memory region is cacheable. */
#define DMM_IS_REG_CACHEABLE(node_id) \
COND_CODE_1(CONFIG_DCACHE, \
(COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_attr), \
((DT_PROP(node_id, zephyr_memory_attr) & DT_MEM_CACHEABLE)), \
(0))), (0))
#define DMM_IS_REG_CACHEABLE(node_id) \
COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_attr), \
((DT_PROP(node_id, zephyr_memory_attr) & DT_MEM_CACHEABLE)), \
(0))

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soc/nordic/common/dmm.h:33 
-#define DMM_IS_REG_CACHEABLE(node_id)					     \
-	COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_attr),	     \
-		((DT_PROP(node_id, zephyr_memory_attr) & DT_MEM_CACHEABLE)), \
-		(0))
+#define DMM_IS_REG_CACHEABLE(node_id)                                                              \
+	COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_attr),                                 \
+		    ((DT_PROP(node_id, zephyr_memory_attr) & DT_MEM_CACHEABLE)), (0))
/* Determine required alignment of the data buffers in specified memory region.
* Cache line alignment is required if region is cacheable and data cache is enabled.
*/
#define DMM_REG_ALIGN_SIZE(node_id) \
(DMM_IS_REG_CACHEABLE(node_id) ? CONFIG_DCACHE_LINE_SIZE : sizeof(uint8_t))

#else

#define DMM_IS_REG_CACHEABLE(node_id) 0
#define DMM_REG_ALIGN_SIZE(node_id) (sizeof(uint8_t))

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soc/nordic/common/dmm.h:44 
-#define DMM_REG_ALIGN_SIZE(node_id) (sizeof(uint8_t))
+#define DMM_REG_ALIGN_SIZE(node_id)   (sizeof(uint8_t))
#endif /* CONFIG_DCACHE */

/* Determine required alignment of the data buffers in memory region
* associated with specified device node.
*/
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