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mit-plv · Jan 10, 2025 · c4d9225 · c4d9225
1 parent a74e8dc
commit c4d9225
Showing 1 changed file with 0 additions and 1 deletion.
diff --git a/compiler/src/compiler/memory_mapped_ext_calls_riscv.v b/compiler/src/compiler/memory_mapped_ext_calls_riscv.v
@@ -139,7 +139,6 @@ Section Riscv.
 
   Definition setReg(reg: Z)(v: word)(regs: Registers): Registers :=
     if ((0 <? reg) && (reg <? 32)) then map.put regs reg v else regs.
-  Print riscv_primitive.
 
   Definition interpret_action (a : riscv_primitive) (mach : RiscvMachine) :
     (primitive_result a -> RiscvMachine -> Prop) -> (RiscvMachine -> Prop) -> Prop :=