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Revert "Add r to make module name factorizer"
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This reverts commit db6e356.
It is not allowed to rename the top module after submission.
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marnovandermaas committed Aug 4, 2023
1 parent 281df8e commit 29c3579
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Showing 5 changed files with 6 additions and 6 deletions.
4 changes: 2 additions & 2 deletions info.yaml
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Expand Up @@ -6,10 +6,10 @@ project:
# If using an HDL, set wokwi_id as 0 and uncomment and list your source files here.
# Source files must be in ./src and you must list each source file separately
source_files:
- tt_um_marno_factorizer.v
- tt_um_marno_factorize.v
- seg7decoder.v
- factorizer.v
top_module: "tt_um_marno_factorizer" # Put the name of your top module here, must start with "tt_um_". Make it unique by prepending your github username
top_module: "tt_um_marno_factorize" # Put the name of your top module here, must start with "tt_um_". Make it unique by prepending your github username

# How many tiles your design occupies? A single tile is about 167x108 uM.
tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 4x2 or 8x2
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2 changes: 1 addition & 1 deletion src/Makefile
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Expand Up @@ -9,7 +9,7 @@ TOPLEVEL_LANG ?= verilog
ifneq ($(GATES),yes)

# this is the only part you should need to modify:
VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/tt_um_marno_factorizer.v $(PWD)/seg7decoder.v $(PWD)/factorizer.v
VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/tt_um_marno_factorize.v $(PWD)/seg7decoder.v $(PWD)/factorizer.v

else

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2 changes: 1 addition & 1 deletion src/tb.v
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Expand Up @@ -29,7 +29,7 @@ module tb ();
wire ena;

// Instantiate the DUT with lower MAX_COUNT for a faster sim
tt_um_marno_factorizer #(.MAX_COUNT(1000)) tt_um_marno_factorizer (
tt_um_marno_factorize #(.MAX_COUNT(1000)) tt_um_seven_segment_seconds (
`ifdef GL_TEST
.VPWR( 1'b1),
.VGND( 1'b0),
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2 changes: 1 addition & 1 deletion src/test.py
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Expand Up @@ -110,7 +110,7 @@ async def test_factor(dut):
list_of_primes = [2, 3, 5, 7, 11, 13, 17, 19]

max_input_value = 0xFF
dut._log.info("check factoring logic")
dut._log.info("check factorize logic")
# Run through all possible inputs
for i in range(1, max_input_value):
expected_factors = 0x00
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@@ -1,6 +1,6 @@
`default_nettype none

module tt_um_marno_factorizer #( parameter MAX_COUNT = 24'd10_000_000 ) (
module tt_um_marno_factorize #( parameter MAX_COUNT = 24'd10_000_000 ) (
input wire [7:0] ui_in, // Dedicated inputs - connected to the input switches
output wire [7:0] uo_out, // Dedicated outputs - connected to the 7 segment display
input wire [7:0] uio_in, // IOs: Bidirectional Input path
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