board/nucleo-h563zi: Add HSE option

Add an option to use HSE on the Nucleo-H563ZI with board modification. This is enabled through board Kconfig. It supplies the same PLL output frequencies using the HSE instead of HSI, for significantly more precise clocks.
lupyuen2 · Dec 3, 2024 · 9b52710 · 9b52710
1 parent 5cd3eed
commit 9b52710
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Showing 3 changed files with 59 additions and 1 deletion.
diff --git a/boards/arm/stm32h5/nucleo-h563zi/Kconfig b/boards/arm/stm32h5/nucleo-h563zi/Kconfig
@@ -5,4 +5,15 @@
 
 if ARCH_BOARD_NUCLEO_H563ZI
 
+config STM32H5_USE_HSE
+	bool "Use on-board HSE"
+	default n
+	---help---
+		Use the supplied on-board 25 MHz HSE. If selected, board.h must supply
+		appropriate clock setup. Requires board modification: 
+			- SB3 and SB4 ON
+			- SB49 OFF
+			- SB48 and SB50 OFF (Default)
+			- C69 and C70 ON, 5.6 pF (Default)
+
 endif
diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig
@@ -17,7 +17,7 @@ CONFIG_ARCH_CHIP_STM32H5=y
 CONFIG_ARCH_INTERRUPTSTACK=2048
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV8M_STACKCHECK=y
-CONFIG_BOARD_LOOPSPERMSEC=8499
+CONFIG_BOARD_LOOPSPERMSEC=9251
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_ASSERTIONS=y
 CONFIG_DEBUG_FEATURES=y

diff --git a/boards/arm/stm32h5/nucleo-h563zi/include/board.h b/boards/arm/stm32h5/nucleo-h563zi/include/board.h
@@ -58,6 +58,51 @@
 #define STM32_LSI_FREQUENCY         32000
 #define STM32_LSE_FREQUENCY         32768
 
+#ifdef CONFIG_STM32H5_USE_HSE
+
+#define STM32_HSE_FREQUENCY     25000000ul
+#define STM32_BOARD_USEHSE
+
+/* PLL1 config: Use to generate 250 MHz system clock
+ *  With HSE Freq = 25 MHz
+ */
+
+#define STM32_PLLCFG_PLL1CFG     (RCC_PLL1CFGR_PLL1SRC_HSE  | \
+                                  RCC_PLL1CFGR_PLL1RGE_4_8M | \
+                                  RCC_PLL1CFGR_PLL1M(5) | \
+                                  RCC_PLL1CFGR_PLL1PEN | \
+                                  RCC_PLL1CFGR_PLL1QEN | \
+                                  RCC_PLL1CFGR_PLL1REN)
+#define STM32_PLLCFG_PLL1N        RCC_PLL1DIVR_PLL1N(100)
+#define STM32_PLLCFG_PLL1P        RCC_PLL1DIVR_PLL1P(2)
+#define STM32_PLLCFG_PLL1Q        RCC_PLL1DIVR_PLL1Q(2)
+#define STM32_PLLCFG_PLL1R        RCC_PLL1DIVR_PLL1R(2)
+#define STM32_PLLCFG_PLL1DIVR     (STM32_PLLCFG_PLL1N | \
+                                   STM32_PLLCFG_PLL1P | \
+                                   STM32_PLLCFG_PLL1Q | \
+                                   STM32_PLLCFG_PLL1R)
+
+#define STM32_VC01_FRQ            ((STM32_HSE_FREQUENCY / 5) * 100)
+#define STM32_PLL1P_FREQUENCY     (STM32_VCO1_FRQ / 2)
+#define STM32_PLL1Q_FREQUENCY     (STM32_VCO1_FRQ / 2)
+#define STM32_PLL1R_FREQUENCY     (STM32_VCO1_FRQ / 2)
+
+/* PLL2 config: Need to use for max ADC speed. */
+
+#define STM32_PLLCFG_PLL2CFG      (RCC_PLL2CFGR_PLL2SRC_HSE | \
+                                   RCC_PLL2CFGR_PLL2RGE_4_8M | \
+                                   RCC_PLL2CFGR_PLL2M(5) | \
+                                   RCC_PLL2CFGR_PLL2REN)
+#define STM32_PLLCFG_PLL2N         RCC_PLL2DIVR_PLL2N(60)
+#define STM32_PLLCFG_PLL2R         RCC_PLL2DIVR_PLL2R(4)
+#define STM32_PLLCFG_PLL2DIVR     (STM32_PLLCFG_PLL2N | \
+                                   STM32_PLLCFG_PLL2R)
+
+#define STM32_VCO2_FRQ            ((STM32_HSE_FREQUENCY / 5) * 60)
+#define STM32_PLL2R_FREQUENCY     (STM32_VCO2_FRQ / 4)
+
+#else
+
 #define STM32_BOARD_USEHSI       1
 #define STM32_BOARD_HSIDIV       RCC_CR_HSIDIV(1)
 #define STM32_HSI_FREQUENCY      32000000ul
@@ -101,6 +146,8 @@
 #define STM32_VCO2_FRQ            ((STM32_HSI_FREQUENCY / 8) * 75)
 #define STM32_PLL2R_FREQUENCY     (STM32_VCO2_FRQ / 4)
 
+#endif /* CONFIG_STM32H5_USE_HSE*/
+
 /* Enable CLK48; get it from HSI48 */
 
 #if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_RNG)