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Add Verilator simulation output to git ignore
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Git should ignore fst files generated by Verilator and also the
`pcount.csv` file which outputs CPU statistics from the simulation.
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marnovandermaas committed Jan 18, 2024
1 parent 14170b9 commit f640161
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2 changes: 2 additions & 0 deletions .gitignore
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Expand Up @@ -2,3 +2,5 @@ book/
build/
.venv/
target/
*.fst
sonata_system_pcount.csv

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