Update lowrisc_ibex to lowRISC/cheriot-ibex@091ccfc3

Update code from upstream repository
https://github.com/lowrisc/cheriot-ibex.git to revision
091ccfc3ce5c9c8dad4acfe200ee45b9401e6a9c

* [rtl] Remove stray comma (Greg Chadwick)
* [rtl] Enable use of ICache with ibexc_top (Greg Chadwick)
* [util] Update check_tool_requirements.py (Gary Guo)
* Update lowrisc_ip to lowRISC/opentitan@f235838a9e (Marno van der
  Maas)
* Added patch to remove alert prim from all group (Marno van der Maas)
* [vendor] Patch updated based on OpenTitan/36a2d3c (Marno van der
  Maas)
* [dv] Alter cov_merge.tcl patch so icache coverage collection works
  (Greg Chadwick)
* Add patch for lowrisc_ip (Harry Callahan)
* [vendor] Update patch file based on upstream OpenTitan (Marno van
  der Maas)
* Feed CHERI errors out to top module (Marno van der Maas)
* Remove prim alert from build (Marno van der Maas)
* Fix tracing (Marno van der Maas)
* Update two port RAM for Sonata (Marno van der Maas)
* Patch reading memory files taken from upstream (Marno van der Maas)
* Various Verilator lint patches (Marno van der Maas)
* Use ibexc_top since that is used in SAFE (Marno van der Maas)
* Add FPGA primitives (Marno van der Maas)
* fixed cheri_csr_always_ok (missing h counters) in ibex_decoder
  (Kunyan Liu)
* updated functional coverage, minor RTL cleanup (rf_we) (Kunyan Liu)
* updated dv/cheriot/tests for the new forward/backward sentry types
  (Kunyan Liu)
* added support for the new forward/backward sentry types (Kunyan Liu)
* more exception-related assertion fixes in ibex_controller (Kunyan
  Liu)
* fixed IbexDontSkipExceptionReq assertion in controller (Kunyan Liu)
* added illegal_regs_cheri to decoder (generate exceptions for regaddr
  > 15) (Kunyan Liu)
* added handling for pc wraparound case in if_stage (issue
  lowrisc/cheriot-ibex#34) (Kunyan Liu)
* added coremark test (Kunyan Liu)
* checking in sanity tests (Kunyan Liu)
* Update README.md (Kunyan Liu)
* fixed illegal instruction warning in controller (Kunyan Liu)
*  added CSR cheri safe-list (no ASR) access feature (Kunyan Liu)
* removed speculative fetching for cjal/cjalr, rvfi and assertion
  fixes (Kunyan Liu)
* fixed mprv (see cheriot-ibex issue lowrisc/cheriot-ibex#35) and
  data-dependent behavior in fetch_fifo (potential side-channel
  leakage (Kunyan Liu)
* fixed FV issues (pcc2mepcc, csr/mret ASR permission fault, etc)
  (Kunyan Liu)
* updated core_ibex_fcov (added csethigh) (Kunyan Liu)
* Ignore build directory (Marno van der Maas)
* Fix reference to rst_ni in tb code (Marno van der Maas)
* Fix assignments in memory model (Marno van der Maas)
* Add missing files for Verlator build (Marno van der Maas)
* Add flags for Verilator version 5 (Marno van der Maas)
* fixed mtcc/mepcc legalization to match sail (Kunyan Liu)
* fixed more exception handling priority issues (Kunyan Liu)
* checked in more dv/cheriot files (Kunyan Liu)
* added csethigh insn and updated test case (Kunyan Liu)

Signed-off-by: Greg Chadwick <[email protected]>

vendor/lowrisc_ibex.lock.hjson

@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/lowrisc/cheriot-ibex.git
-    rev: 3081de9f03af988bf2c5200b9787d81c6a2d8bc7
+    rev: 091ccfc3ce5c9c8dad4acfe200ee45b9401e6a9c
   }
 }

vendor/lowrisc_ibex/README.md

@@ -21,15 +21,15 @@ Use of Microsoft trademarks or logos in modified versions of this project must n
 Any use of third-party trademarks or logos are subject to those third-party's policies.
 
 ## Introduction
-cheriot-ibex is 32-bit RISC-V microcontroller which implements the CHERIoT ISA extension in addition to RV32IMCB. Same as the original ibex core, the design can be configured either with a 2-stage or a 3-stage pipeline. It has passed preliminary simulation and FPGA validation, and is currently undergoing  further verification as well as PPA analysis at Microsoft.
+cheriot-ibex is 32-bit RISC-V microcontroller which implements the CHERIoT ISA extension in addition to RV32IMCB. Same as the original ibex core, the design can be configured either with a 2-stage or a 3-stage pipeline. It has passed preliminary simulation, formal verification and FPGA validation, and is currently under further verification at Microsoft.
 
 ![image](https://github.com/microsoft/cheriot-ibex/assets/116126768/51b768f5-a528-4d93-bce4-392ac2fe1488)
 
 ## CHERIoT ISA support
 
 cheriot-ibex supports all instructions listed in the [CHERIoT ISA specification](https://github.com/microsoft/cheriot-sail/tree/main/archdoc), including
 
-- To query or test capabilities: cgetaddr, cgetbase, cgetlen, cgetperm, cgettag, cgettop, cgettype, ctestsubset, csetequalexact, csub
+- To query or test capabilities: cgetaddr, cgetbase, cgethigh, cgetlen, cgetperm, cgettag, cgettop, cgettype, ctestsubset, csetequalexact, csub, csethigh
 - To modify or derive capabilities: auicgp, auipcc, candperm, ccleartag, cincaddr, cincaddrimm, cmove, cram, crrl, csetaddr, csetbounds, csetboundsexact, csetboundsimm, cseal, cunseal
 - To load/store capabilities from memory: clc, csc
 - To control the program flow: cjal, cjalr
@@ -120,7 +120,7 @@ A PPA study conducted at Microsoft shows that cheriot-ibex is similar to the ori
 
 cheriot-ibex (configured as 3-stage pipeline) has been synthesized successfully using Synopsys DC-topo at 250MHz using TSMC 28nm (28LP) libraries (ss 1.03v) and 550MHz using TSMC 5nm (N5) libraries (ss 0.6v). Timing is mostly limited by TCM read access time (which approaches 1.6ns in the N5 case). 
 
-The design area is ~60k gate equivalents (~25% more the original ibex design). Both dynamic and leakage power are shown as similar to the original ibex design.
+The design area is ~60k gate equivalents. Both dynamic and leakage power are shown as similar to the original ibex design.
 
 
 ## Build the design for simulation and emulation

vendor/lowrisc_ibex/dv/cheriot/run/.gitignore

@@ -0,0 +1 @@
+obj_dir/

vendor/lowrisc_ibex/dv/cheriot/run/all.f

@@ -1,5 +1,4 @@
--Wno-WIDTHEXPAND
--Wno-WIDTHTRUNC
+-Wno-WIDTH
 -Wno-USERFATAL
 -Wno-UNOPTFLAT
 -Wno-IMPLICIT
@@ -8,6 +7,7 @@
 -Wno-UNSIGNED
 -Wno-INITIALDLY
 -Wno-CASEX
+--timing
 +incdir+$rtlRoot
 +incdir+$primRoot
 +incdir+$dvutilsRoot
@@ -18,6 +18,7 @@
 $rtlRoot/cheri_pkg.sv
 $rtlRoot/ibex_pkg.sv
 $rtlRoot/ibex_tracer_pkg.sv
+$verifRoot/tb/cheriot_dv_pkg.sv
 $rtlRoot/cheri_decoder.sv
 $rtlRoot/cheri_ex.sv
 $rtlRoot/cheri_regfile.sv
@@ -48,5 +49,9 @@
 $rtlRoot/ibexc_top.sv
 $rtlRoot/ibex_tracer.sv
 $rtlRoot/ibexc_top_tracing.sv
-$verifRoot/tb/mem_model.sv
+$verifRoot/tb/data_mem_model.sv
+$verifRoot/tb/dii_if.sv
+$verifRoot/tb/instr_mem_model.sv
+$verifRoot/tb/mem_monitor.sv
+$verifRoot/tb/mem_obi_if.sv
 $verifRoot/tb/tb_cheriot_top.sv

vendor/lowrisc_ibex/dv/cheriot/run/ibexc.vcs.f

@@ -39,12 +39,15 @@
 $rtlRoot/ibexc_top.sv
 $rtlRoot/ibex_tracer.sv
 $rtlRoot/ibexc_top_tracing.sv
+$verifRoot/tb/cheriot_dv_pkg.sv
 $verifRoot/tb/mem_obi_if.sv
 $verifRoot/tb/instr_mem_model.sv
 $verifRoot/tb/data_mem_model.sv
+$verifRoot/tb/mem_monitor.sv
 $verifRoot/tb/dii_if.sv
 $verifRoot/tb/intr_gen.sv
 $verifRoot/tb/cap_err_gen.sv
+$verifRoot/tb/tbre_bg_gen.sv
 $verifRoot/tb/tb_cheriot_top.sv
 $verifRoot/tb/module_dv_ext.sv
 $verifRoot/tb/core_ibex_fcov_if.sv

vendor/lowrisc_ibex/dv/cheriot/run/vcscomp2

@@ -3,5 +3,4 @@ export primRoot=../../../vendor/lowrisc_ip/ip/prim/rtl
 export dvutilsRoot=../../../vendor/lowrisc_ip/dv/sv/dv_utils
 export verifRoot=..
 
-#vnc run  -Ir -wl -r  vcs  RAM/64000 x86_64 redhat7 -- vcs -full64 -sverilog +systemverilogext+sv -timescale=1ns/1ps -debug_acc+all -f ibexc.vcs.f
-vcs -full64 -sverilog +systemverilogext+sv -timescale=1ns/1ps -debug_acc+all -f ibexc.vcs.f
+vcs -full64 -sverilog -xlrm uniq_prior_final +systemverilogext+sv -timescale=1ns/1ps -debug_acc+all -f ibexc.vcs.f $*

vendor/lowrisc_ibex/dv/cheriot/scripts/build_coremark.sh

@@ -0,0 +1,46 @@
+#!/bin/bash 
+
+set -e 
+
+source ../scripts/common_setup.sh
+mkdir -p work
+cd work
+
+pwd
+
+export TESTNAME=coremark
+export CSRC=../csrc_cheri
+export SRC=../coremark
+export S_FILES="$CSRC/startup.S"
+export OBJ_FILES="startup.o"
+export C_COMMON="$CSRC/cstart.c $CSRC/util.c"
+export C_FILES="$C_COMMON $SRC/core_main.c $SRC/core_list_join.c $SRC/core_matrix.c $SRC/core_util.c $SRC/core_state.c $SRC/cheri/core_portme.c $SRC/cheri/ee_printf.c $SRC/cheri/cheri_atest.S"
+export LD_FILE="../link_coremark.ld"
+export ELF_OUTPUT=$TESTNAME.elf
+export BIN_OUTPUT=$TESTNAME.bin
+export HEX_OUTPUT=$TESTNAME.vhx
+
+# run the compile 
+BASE_FLAGS="-target riscv32-unknown-unknown -mcpu=cheriot -mabi=cheriot -mxcheri-rvc -Oz -g -nostdlib"
+ADDON_CFLAGS="-DNDEBUG -DCOREMARK -I$SRC -I$CSRC -I$SRC/cheri"  
+
+#RUN_CFLAGS="-DVALIDATION_RUN=1 -DITERATIONS=1 -DCLOCKS_PER_SEC=10000000" 
+RUN_CFLAGS="-DPERFORMACE_RUN=1 -DITERATIONS=1 -DCLOCKS_PER_SEC=10000000" 
+CLANG_FLAGS="$BASE_FLAGS $ADDON_CFLAGS $RUN_CFLAGS" 
+
+echo "compile and linking.."
+echo $CLANG_FLAGS
+$CLANG $BASE_FLAGS -c $S_FILES
+$CLANG $CLANG_FLAGS  -DFLAGS_STR="\"$CLANG_FLAGS\"" -T$LD_FILE -o $ELF_OUTPUT $C_FILES $OBJ_FILES
+
+$GCC_OBJCOPY -O binary -S $ELF_OUTPUT $BIN_OUTPUT
+
+$BIN2HEX $BIN_OUTPUT > $HEX_OUTPUT
+
+echo "Generating disassembled text.."
+$LLVM_HOME/llvm-objdump -xdCS --mcpu=cheriot $ELF_OUTPUT > $TESTNAME.dis
+
+echo "Copying binaries to run area.."
+cp $HEX_OUTPUT ../../run/bin
+cp $ELF_OUTPUT ../../run/bin
+