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Hardwire CHERI to enable
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marnovandermaas authored and HU90m committed May 23, 2024
1 parent 865f002 commit 21f4c1a
Showing 1 changed file with 2 additions and 12 deletions.
14 changes: 2 additions & 12 deletions rtl/fpga/top_sonata.sv
Original file line number Diff line number Diff line change
Expand Up @@ -162,19 +162,9 @@ module top_sonata (
wire scl1_i = scl1 & rph_g3_scl & mb6;
wire sda1_i = sda1 & rph_g2_sda & mb5;

// DIP switches are OFF by default and employ a pull up, which means CHERI shall enabled by
// default; sample this once when leaving reset as a development aid during bring up.
// Enable CHERI by default.
logic enable_cheri;
logic cheri_decided;
always_ff @(posedge clk_sys or negedge rst_sys_n) begin
if (!rst_sys_n) begin
cheri_decided <= 1'b0;
enable_cheri <= 1'b1;
end else if (!cheri_decided) begin
enable_cheri <= usrSw[7];
cheri_decided <= 1'b1;
end
end
assign enable_cheri = 1'b1;

sonata_system #(
.GpiWidth ( 13 ),
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