Reduce mtvec alignment requirement #427
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| @@ -378,6 +378,7 @@ module ibex_cs_registers #( | |||
| mepc_d = mepc_q; | |||
| mcause_d = mcause_q; | |||
| mtval_d = mtval_q; | |||
| // TODO Should this assignment use boot_addr_i[31:1]? [7:2] always 6'b0 | |||
RISC-V Privileged Spec v1.11 allows BASE filed of mtvec to be 4-byte aligned. Update the assignment and usage of mtvec to use 4-byte aligned addresses. This fixes `I-EBREAK` and `I-ECALL` tests of RISC-V compliance failures reported in lowRISC#100.
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Thanks @towoe for your PR.
It is correct that the RISC-V Privileged Spec allows for 4-byte aligned mtvec but it does not require it.
I do not agree with the proposed changes, and I don't think we should allow 4-byte aligned values in mtvec. Either it requires the instantiation of an adder in the IF stage to compute the correct address for interrupts. Or, if the core ignores the LSBs of mtvec for interrupts (as you are suggesting with this PR), the LSBs of mtvec are ignored for interrupts but not for exceptions which is not programmer friendly.
IMO this must be solved upstream in the compliance suite.
|
Thanks @vogelpi for the feedback. |
RISC-V Privileged Spec v1.11 allows BASE filed of mtvec to be 4-byte
aligned.
Update the assignment and usage of mtvec to use 4-byte aligned
addresses.
This fixes
I-EBREAKandI-ECALLtests of RISC-V compliance failuresreported in #100.