Add support for RISCOF based checks

azure-pipelines.yml

@@ -86,6 +86,7 @@ jobs:
       git clone https://github.com/riscv/riscv-compliance.git
       cd riscv-compliance
       git checkout "$RISCV_COMPLIANCE_GIT_VERSION"
+      git worktree add ../riscv-compliance-v2 --detach "$RISCV_COMPLIANCE_GIT_VERSION2"
     displayName: Get RISC-V Compliance test suite
 
   # Run Ibex RTL CI per supported configuration

ci/ibex-rtl-ci-steps.yml

@@ -65,3 +65,17 @@ steps:
         done
         exit $fail
       displayName: Run RISC-V Compliance test for Ibex RV32IMC for ${{ config }}
+
+    - bash: |
+        # Run compliance test suite
+        export IBEX_SIMULATOR=$PWD/build/lowrisc_ibex_ibex_riscv_compliance_0.1/sim-verilator/Vibex_riscv_compliance
+        export RISCV_PREFIX=riscv32-unknown-elf-
+        riscof run --config dv/riscof/config.ini --suite build/riscv-compliance-v2/riscv-test-suite --no-browser
+        if [ $? != 0 ]; then
+          echo -n "##vso[task.logissue type=error]"
+          echo "RISCOF compliance test suite failure. Ignoring exit condition."
+          exit 0
+        fi
+
+      displayName: Run RISC-V Compliance Version 2 test for Ibex RV32IMC for ${{ config }}
+      continueOnError: true

ci/install-build-deps.sh

@@ -32,16 +32,16 @@ case "$ID-$VERSION_ID" in
     $SUDO_CMD sh -c "echo 'deb http://download.opensuse.org/repositories/home:/phiwag:/edatools/xUbuntu_$VERSION_ID/ /' > /etc/apt/sources.list.d/edatools.list"
     $SUDO_CMD apt-get update
 
+    # Uninstall distribution-provided version to get a newer version through pip
+    $SUDO_CMD apt-get remove -y python3-yaml
+
     # Packaged dependencies
-    # Install python3-yaml through apt to get a version with libyaml bindings,
-    # which is significantly faster than the pure Python version.
     $SUDO_CMD apt-get install -y \
         device-tree-compiler \
         python3 \
         python3-pip \
         python3-setuptools \
         python3-wheel \
-        python3-yaml \
         srecord \
         zlib1g-dev \
         git \

ci/vars.yml

@@ -10,6 +10,7 @@ variables:
   RISCV_TOOLCHAIN_TAR_VERSION: "20200904-1"
   RISCV_TOOLCHAIN_TAR_VARIANT: "lowrisc-toolchain-gcc-rv32imcb"
   RISCV_COMPLIANCE_GIT_VERSION: "844c6660ef3f0d9b96957991109dfd80cc4938e2"
+  RISCV_COMPLIANCE_GIT_VERSION2: "65cd9556846c60608c06e9db22ab573c1e86fe6b"
   VERIBLE_VERSION: "v0.0-705-g75249d0"
   # lowRISC-internal version numbers of Ibex-specific Spike builds.
   SPIKE_IBEX_VERSION: "20201023-git-255bf1cacc599b1413438c269100f3ecd0eb3352"

dv/riscof/README.md

@@ -0,0 +1,87 @@
+# RISC-V compliance check
+
+Verify that Ibex conforms to the RISC-V specification by running a compliance
+check.
+
+Version 2 of [riscv-compliance](https://github.com/riscv/riscv-compliance)
+started to integrate with [RISCOF](https://gitlab.com/incoresemi/riscof) and
+aims to provide the new structure with [version
+3](https://github.com/riscv/riscv-compliance/issues/165#issuecomment-760121860).
+
+Each core provides a Python plugin which handles the required setup,
+compilation and execution step. This plugin is invoked by RISCOF.
+
+A simulation of [Ibex](../riscv_compliance/README.md) is used to execute the
+instruction checks.
+
+RISCOF is not yet finished, some checks will fail and the configuration
+provided by [config.ini](config.ini) will only compare the output from Ibex
+to a fixed reference.
+
+## Run RISCOF RISC-V Compliance
+
+### Requirements
+
+In addition to [steps 0, 1 and
+2](../riscv_compliance/README.md#how-to-run-risc-v-compliance-on-ibex) the
+RISCOF package must be installed:
+
+```sh
+pip3 install --user -U riscof
+```
+
+### Running the checks
+
+```sh
+cd $IBEX_REPO_BASE
+export RISCV_PREFIX=riscv32-unknown-elf-
+export IBEX_SIMULATOR=$PWD/build/lowrisc_ibex_ibex_riscv_compliance_0.1/sim-verilator/Vibex_riscv_compliance
+riscof run --config dv/riscof/config.ini  --suite /path/to/riscv-compliance/riscv-test-suite --no-browser
+```
+
+## Additional notes to the current status
+
+### Changing the reference model
+
+In order to compare the results produced by Ibex to another model the file
+`config.ini` must be updated.
+
+To use for example [Sail](https://github.com/rems-project/sail-riscv) update
+and append with:
+
+```
+[RISCOF]
+ReferencePlugin=sail_cSim
+ReferencePluginPath=/path/to/sail_cSim
+
+[sail_cSim]
+pluginpath=/path/to/sail_cSim
+```
+
+### Failing checks
+
+Due to some current restrictions in the test suite some checks fail:
+- Branch and jump fail due to
+  [memory size](https://github.com/riscv/riscv-compliance/issues/157)
+  restrictions.
+- Incorrect selection of
+  [RV64](https://github.com/riscv/riscv-compliance/pull/168) tests.
+- [break](https://github.com/riscv/riscv-compliance/issues/145)
+- [ecall](https://github.com/riscv/riscv-compliance/issues/146)
+- [misalign ldst](https://github.com/riscv/riscv-compliance/issues/147)
+- [misalign jmp](https://github.com/riscv/riscv-compliance/issues/148)
+
+
+### Restrictions
+
+- Due to backwards compatibility riscv-compliance testsuite will report some
+  [warnings](https://github.com/riscv/riscv-compliance/issues/169).
+- Not compatible with
+  [RV32E](https://github.com/riscv/riscv-compliance/issues/142).
+
+
+### Future updates
+
+When the riscv-compliance framework v1 is not longer used, the riscv-compliance
+target can be changed and the memory can be moved to a more sensible location
+(e.g. `0x8000_0000`).

dv/riscof/config.ini

@@ -0,0 +1,13 @@
+[RISCOF]
+ReferencePlugin=rc_reference
+ReferencePluginPath=rc_reference
+DUTPlugin=Ibex
+DUTPluginPath=ibex
+
+[Ibex]
+pluginpath=ibex
+ispec=ibex/ibex_small_isa.yaml
+pspec=ibex/ibex_platform.yaml
+
+[rc_reference]
+riscvTestSuite=reference_signature

dv/riscof/ibex/__init__.py

@@ -0,0 +1,2 @@
+from pkgutil import extend_path
+__path__ = extend_path(__path__, __name__)

dv/riscof/ibex/env/link.ld

@@ -0,0 +1,22 @@
+OUTPUT_ARCH( "riscv" )
+ENTRY(rvtest_entry_point)
+
+SECTIONS {
+  . = 0x00000000;
+  .text.trap : { *(.text.trap) }
+
+  . = . + 0x00000080;
+  .text.init : { *(.text.init) }
+
+  . = ALIGN(0x1000);
+  .tohost : { *(.tohost) }
+
+  . = ALIGN(0x1000);
+  .text : { *(.text) }
+
+  . = ALIGN(0x1000);
+  .data : { *(.data) }
+  .data.string : { *(.data.string)}
+  .bss : { *(.bss) }
+  _end = .;
+}

dv/riscof/ibex/env/model_test.h

@@ -0,0 +1,101 @@
+#ifndef _COMPLIANCE_MODEL_H
+#define _COMPLIANCE_MODEL_H
+
+//-----------------------------------------------------------------------
+// Model specific Macros
+//-----------------------------------------------------------------------
+
+#define TESTUTIL_BASE 0x20000
+#define TESTUTIL_ADDR_HALT (TESTUTIL_BASE + 0x0)
+#define TESTUTIL_ADDR_BEGIN_SIGNATURE (TESTUTIL_BASE + 0x4)
+#define TESTUTIL_ADDR_END_SIGNATURE (TESTUTIL_BASE + 0x8)
+
+// clang-format off
+// clang-format tries to combine .pushsection and .tohost to one word.
+#define RVMODEL_DATA_SECTION             \
+  .pushsection .tohost, "aw", @progbits; \
+  .align 8;                              \
+  .global tohost;                        \
+  tohost:                                \
+  .dword 0;                              \
+  .align 8;                              \
+  .global fromhost;                      \
+  fromhost:                              \
+  .dword 0;                              \
+  .popsection;                           \
+  .align 8;                              \
+  .global begin_regstate;                \
+  begin_regstate:                        \
+  .word 128;                             \
+  .align 8;                              \
+  .global end_regstate;                  \
+  end_regstate:                          \
+  .word 4;
+// clang-format on
+
+// RV_COMPLIANCE_HALT
+#define RVMODEL_HALT                                    \
+  li x1, 1;                                             \
+  .globl write_tohost;                                  \
+  write_tohost:                                         \
+  sw x1, tohost, t5;                                    \
+  la t0, begin_signature;                               \
+  li t1, TESTUTIL_ADDR_BEGIN_SIGNATURE;                 \
+  sw t0, 0(t1);                                         \
+  /* tell simulation about location of end_signature */ \
+  la t0, end_signature;                                 \
+  li t1, TESTUTIL_ADDR_END_SIGNATURE;                   \
+  sw t0, 0(t1);                                         \
+  /* dump signature and terminate simulation */         \
+  li t0, 1;                                             \
+  li t1, TESTUTIL_ADDR_HALT;                            \
+  sw t0, 0(t1);                                         \
+  self_loop:                                            \
+  j self_loop;
+
+#define RVMODEL_BOOT  // Define the boot sequence for the implementation here.
+
+// RV_COMPLIANCE_DATA_BEGIN
+// Change the definition in the following macros if the implementation expects
+// different labels for identifying the signature section.
+// clang-format off
+// clang-format tries to combine RVMODEL_DATA_SECTION and .global
+#define RVMODEL_DATA_BEGIN \
+  RVMODEL_DATA_SECTION     \
+  .global begin_signature; \
+  begin_signature:
+// clang-format on
+
+// RV_COMPLIANCE_DATA_END
+#define RVMODEL_DATA_END \
+  .global end_signature; \
+  end_signature:
+
+// Define the IO macros as required.
+// RVTEST_IO_INIT
+#define RVMODEL_IO_INIT
+
+// RVTEST_IO_WRITE_STR
+#define RVMODEL_IO_WRITE_STR(_R, _STR)
+
+// RVTEST_IO_CHECK
+#define RVMODEL_IO_CHECK()
+
+// RVTEST_IO_ASSERT_GPR_EQ
+#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I)
+
+// RVTEST_IO_ASSERT_SFPR_EQ
+#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
+
+// RVTEST_IO_ASSERT_DFPR_EQ
+#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
+
+#define RVMODEL_SET_MSW_INT
+
+#define RVMODEL_CLEAR_MSW_INT
+
+#define RVMODEL_CLEAR_MTIMER_INT
+
+#define RVMODEL_CLEAR_MEXT_INT
+
+#endif  // _COMPLIANCE_MODEL_H

dv/riscof/ibex/ibex_platform.yaml

@@ -0,0 +1,4 @@
+nmi:
+  label: nmi_vector
+reset:
+  label: reset_vector

dv/riscof/ibex/ibex_small_isa.yaml

@@ -0,0 +1,28 @@
+hart_ids: [0]
+hart0:
+  ISA: RV32IMCUZicsr_Zifencei
+  User_Spec_Version: '2.3'
+  supported_xlen: [32]
+  physical_addr_sz: 32
+  misa:
+   reset-val: 0x40101104
+   rv32:
+     accessible: true
+     mxl:
+       implemented: true
+       type:
+           warl:
+              dependency_fields: []
+              legal:
+                - mxl[1:0] in [0x1]
+              wr_illegal:
+                - unchanged
+     extensions:
+       implemented: true
+       type:
+           warl:
+              dependency_fields: []
+              legal:
+                - extensions[25:0] in [0x0000000:0x3FFFFFF]
+              wr_illegal:
+                - unchanged