Enable bitstream generation with flat routing

[fkosar-ql]

Motivate of the pull request

• To address an existing issue. If so, please provide a link to the issue:
• Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

What does this pull request change?

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.

[tangxifan]

@fkosar-ql Good work on simplifying the codes. I have cleaned up the code conflicts with VTR latest and update the submodule to the latest.

I believe this PR can be merged after code formatting is resolved. The rest of the flat router can be in another PR.

Let me know if this works for you.

[fkosar-ql]

I think we can merge this

[tangxifan]

@fkosar-ql Merged. Please continue the effort on a follow-up PR. Thank you for the contribution.