fix formatting

lnis-uofu · Oct 31, 2024 · e1acc5e · e1acc5e
1 parent cc18704
commit e1acc5e
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Showing 6 changed files with 44 additions and 38 deletions.
diff --git a/openfpga/src/base/openfpga_bitstream_template.h b/openfpga/src/base/openfpga_bitstream_template.h
@@ -45,9 +45,10 @@ int fpga_bitstream_template(T& openfpga_ctx, const Command& cmd,
     openfpga_ctx.mutable_bitstream_manager() = read_xml_architecture_bitstream(
       cmd_context.option_value(cmd, opt_read_file).c_str());
   } else {
-    openfpga_ctx.mutable_bitstream_manager() = build_device_bitstream(
-      g_vpr_ctx, openfpga_ctx, cmd_context.option_enable(cmd, opt_prefer_unused),
-      cmd_context.option_enable(cmd, opt_verbose));
+    openfpga_ctx.mutable_bitstream_manager() =
+      build_device_bitstream(g_vpr_ctx, openfpga_ctx,
+                             cmd_context.option_enable(cmd, opt_prefer_unused),
+                             cmd_context.option_enable(cmd, opt_verbose));
   }
 
   overwrite_bitstream(openfpga_ctx.mutable_bitstream_manager(),

diff --git a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp
@@ -219,9 +219,7 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
     openfpga_ctx.vpr_device_annotation(),
     openfpga_ctx.vpr_clustering_annotation(),
     openfpga_ctx.vpr_placement_annotation(),
-    openfpga_ctx.vpr_bitstream_annotation(),
-    prefer_unused_mux_input,
-    verbose);
+    openfpga_ctx.vpr_bitstream_annotation(), prefer_unused_mux_input, verbose);
   VTR_LOGV(verbose, "Done\n");
 
   /* Create bitstream from routing architectures */
@@ -232,8 +230,8 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
     openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(), vpr_ctx.atom(),
     openfpga_ctx.vpr_device_annotation(), openfpga_ctx.vpr_routing_annotation(),
     vpr_ctx.device().rr_graph, openfpga_ctx.device_rr_gsb(),
-    openfpga_ctx.flow_manager().compress_routing(),
-    prefer_unused_mux_input, verbose);
+    openfpga_ctx.flow_manager().compress_routing(), prefer_unused_mux_input,
+    verbose);
 
   VTR_LOGV(verbose, "Done\n");
 

diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
@@ -185,8 +185,7 @@ static void build_physical_block_pin_interc_bitstream(
   const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
   const VprBitstreamAnnotation& bitstream_annotation,
   const PhysicalPb& physical_pb, t_pb_graph_pin* des_pb_graph_pin,
-  t_mode* physical_mode,
-  const bool& prefer_unused_mux_input,
+  t_mode* physical_mode, const bool& prefer_unused_mux_input,
   const bool& verbose) {
   /* Identify the number of fan-in (Consider interconnection edges of only
    * selected mode) */
@@ -237,8 +236,8 @@ static void build_physical_block_pin_interc_bitstream(
       } else if (AtomNetId::INVALID() == physical_pb.pb_graph_pin_atom_net(
                                            des_pb_id, des_pb_graph_pin)) {
         /* Unmapped output */
-        if(false == circuit_lib.mux_add_const_input(mux_model) &&
-           prefer_unused_mux_input){
+        if (false == circuit_lib.mux_add_const_input(mux_model) &&
+           prefer_unused_mux_input) {
           /* No constant input and fix flag is set
            * Select the first unmapped input */
           auto pin_inputs = pb_graph_pin_inputs(des_pb_graph_pin, cur_interc);
@@ -255,12 +254,13 @@ static void build_physical_block_pin_interc_bitstream(
           /* Couldn't find an unmapped input, use default path ID */
           if (pin_id == pin_inputs.size()) {
             VTR_LOGV_WARN(verbose,
-              "At PhysicalPbId=%d: output is unmapped but all inputs are mapped\n",
+              "At PhysicalPbId=%d: output is unmapped but all"
+              " inputs are mapped\n",
               des_pb_id);
             mux_input_pin_id = DEFAULT_PATH_ID;
           }
           /* or the first input was already unmapped, use default path ID */
-          if(mux_input_pin_id == 0) {
+          if (mux_input_pin_id == 0) {
             mux_input_pin_id = DEFAULT_PATH_ID;
           }
         } else {
@@ -505,8 +505,8 @@ static void build_physical_block_interc_bitstream(
     bitstream_manager, grouped_mem_inst_scoreboard, parent_configurable_block,
     module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx,
     device_annotation, bitstream_annotation, physical_pb_graph_node,
-    physical_pb, CIRCUIT_PB_PORT_OUTPUT, physical_mode,
-    prefer_unused_mux_input, verbose);
+    physical_pb, CIRCUIT_PB_PORT_OUTPUT, physical_mode, prefer_unused_mux_input,
+    verbose);
 
   /* We check input_pins of child_pb_graph_node and its the input_edges
    * Iterate over the interconnections between inputs of physical_pb_graph_node
@@ -981,7 +981,8 @@ static void build_physical_block_bitstream(
           bitstream_manager, grouped_mem_inst_scoreboard,
           grid_configurable_block, module_manager, module_name_map, circuit_lib,
           mux_lib, atom_ctx, device_annotation, bitstream_annotation,
-          border_side, phy_pb, top_pb_id, pb_graph_head, z, prefer_unused_mux_input, verbose);
+          border_side, phy_pb, top_pb_id, pb_graph_head, z,
+          prefer_unused_mux_input, verbose);
       }
     }
   }
@@ -1002,8 +1003,7 @@ void build_grid_bitstream(
   const VprClusteringAnnotation& cluster_annotation,
   const VprPlacementAnnotation& place_annotation,
   const VprBitstreamAnnotation& bitstream_annotation,
-  const bool& prefer_unused_mux_input,
-  const bool& verbose) {
+  const bool& prefer_unused_mux_input, const bool& verbose) {
   VTR_LOGV(verbose, "Generating bitstream for core grids...");
 
   /* Generate bitstream for the core logic block one by one */

diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.h b/openfpga/src/fpga_bitstream/build_grid_bitstream.h
@@ -35,8 +35,7 @@ void build_grid_bitstream(
   const VprClusteringAnnotation& cluster_annotation,
   const VprPlacementAnnotation& place_annotation,
   const VprBitstreamAnnotation& bitstream_annotation,
-  const bool& prefer_unused_mux_input,
-  const bool& verbose);
+  const bool& prefer_unused_mux_input, const bool& verbose);
 
 } /* end namespace openfpga */
 

diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
@@ -102,13 +102,15 @@ static void build_switch_block_mux_bitstream(
     /* Warn if all inputs were mapped */
     if (path_id == DEFAULT_PATH_ID) {
         VTR_LOGV_WARN(verbose, 
-          "At RRNodeId = %d: output is unmapped but all inputs are mapped?", cur_rr_node);
+          "At RRNodeId = %d: output is unmapped but all inputs are mapped?",
+          cur_rr_node);
     }
-    /* If the first input was already unmapped, set path id to default (for compatibility purposes) */
+    /* If the first input was already unmapped, set path id to default
+     * (for compatibility purposes) */
     if (path_id == 0) {
       path_id = DEFAULT_PATH_ID;
     }
-  } /* Keep default path id if output is unmapped but somehow all inputs are mapped */
+  } /* Keep default path id if output is unmapped but all inputs are mapped */
 
   /* Ensure that our path id makes sense! */
   VTR_ASSERT(
@@ -244,7 +246,8 @@ static void build_switch_block_bitstream(
   const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib,
   const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
   const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph,
-  const RRGSB& rr_gsb, const bool& prefer_unused_mux_input, const bool& verbose) {
+  const RRGSB& rr_gsb, const bool& prefer_unused_mux_input,
+  const bool& verbose) {
   /* Iterate over all the multiplexers */
   for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
     SideManager side_manager(side);
@@ -262,7 +265,8 @@ static void build_switch_block_bitstream(
       build_switch_block_interc_bitstream(
         bitstream_manager, sb_config_block, module_manager, module_name_map,
         circuit_lib, mux_lib, rr_graph, atom_ctx, device_annotation,
-        routing_annotation, rr_gsb, side_manager.get_side(), itrack, prefer_unused_mux_input, verbose);
+        routing_annotation, rr_gsb, side_manager.get_side(), itrack,
+        prefer_unused_mux_input, verbose);
     }
   }
 }
@@ -326,29 +330,34 @@ static void build_connection_block_mux_bitstream(
       }
       edge_index++;
     }
-  } else if (false == circuit_lib.mux_add_const_input(mux_model) && prefer_unused_mux_input){
+  } else if (false == circuit_lib.mux_add_const_input(mux_model) &&
+             prefer_unused_mux_input){
     /* If
      * 1. output net is INVALID (unmapped)
      * 2. and we don't have a constant input,
      * 3. and the prefer_unused_mux_input flag is on,
      * then find an unmapped input and connect it to the output net */
-    for (int iedge = driver_rr_edges.size() - 1; iedge >= 0; --iedge){
+    for (size_t iedge = 0; iedge < driver_rr_edges.size(); iedge++){
       RREdgeId edge = driver_rr_edges[iedge];
       RRNodeId driver_node = rr_graph.edge_src_node(edge);
-      if (routing_annotation.rr_node_net(driver_node) == ClusterNetId::INVALID()){
+      if (routing_annotation.rr_node_net(driver_node) ==
+          ClusterNetId::INVALID()){
         path_id = iedge;
         break;
       }
     }
     /* Warn if all inputs are mapped */
-    if(path_id == -1){
-      VTR_LOG_ERROR("At RRNodeId = %d: output is unmapped but all inputs are mapped?", src_rr_node);
+    if (path_id == int(driver_rr_edges.size())) {
+      VTR_LOGV_WARN(verbose,
+        "At RRNodeId = %d: output is unmapped but all inputs are mapped?",
+        src_rr_node);
     }
-    /* If the last input was already unmapped, set path id to default (for compatibility purposes) */
-    if((size_t)path_id == driver_rr_edges.size() - 1){
+    /* If the first input was already unmapped, set path id to default
+     * (for compatibility purposes) */
+    if (path_id == 0) {
       path_id = DEFAULT_PATH_ID;
     }
-  } /* Keep default path id if output is unmapped but somehow all inputs are mapped */
+  } /* Keep default path id if output is unmapped but all inputs are mapped */
 
   /* Ensure that our path id makes sense! */
   VTR_ASSERT(
@@ -640,8 +649,8 @@ static void build_connection_block_bitstreams(
       build_connection_block_bitstream(
         bitstream_manager, cb_configurable_block, module_manager,
         module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation,
-        routing_annotation, rr_graph, rr_gsb, cb_type,
-        prefer_unused_mux_input, verbose);
+        routing_annotation, rr_graph, rr_gsb, cb_type, prefer_unused_mux_input,
+        verbose);
 
       VTR_LOGV(verbose, "\tDone\n");
     }

diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.h b/openfpga/src/fpga_bitstream/build_routing_bitstream.h
@@ -36,8 +36,7 @@ void build_routing_bitstream(
   const VprDeviceAnnotation& device_annotation,
   const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph,
   const DeviceRRGSB& device_rr_gsb, const bool& compact_routing_hierarchy,
-  const bool& prefer_unused_mux_input,
-  const bool& verbose);
+  const bool& prefer_unused_mux_input, const bool& verbose);
 
 } /* end namespace openfpga */