[CIR][CIRGen][Builtin][Neon] Lower neon_vrshl_v and neon_vrshlq_v #1151
+218
−132
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They are rounding shift of vectors, and shift amount is from the least significant byte of the corresponding element of the second input vector. Thus, it is implemented in its own ASM . These make them not suitable to be lowered to CIR ShiftOp though it supports vector type now.