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Use getDiscardableAttr to access discardable attributes #7761

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Use getDiscardableAttr to access discardable attributes #7761

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14 changes: 7 additions & 7 deletions lib/Conversion/FIRRTLToHW/LowerToHW.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3015,11 +3015,11 @@ LogicalResult FIRRTLLowering::visitDecl(RegOp op) {
op.getNameAttr(), innerSym);

// Pass along the start and end random initialization bits for this register.
if (auto randomRegister = op->getAttr("firrtl.random_init_register"))
if (auto randomRegister = op->getDiscardableAttr("firrtl.random_init_register"))
reg->setAttr("firrtl.random_init_register", randomRegister);
if (auto randomStart = op->getAttr("firrtl.random_init_start"))
if (auto randomStart = op->getDiscardableAttr("firrtl.random_init_start"))
reg->setAttr("firrtl.random_init_start", randomStart);
if (auto randomEnd = op->getAttr("firrtl.random_init_end"))
if (auto randomEnd = op->getDiscardableAttr("firrtl.random_init_end"))
reg->setAttr("firrtl.random_init_end", randomEnd);

// Move SV attributes.
Expand Down Expand Up @@ -3056,11 +3056,11 @@ LogicalResult FIRRTLLowering::visitDecl(RegResetOp op) {
resetSignal, resetValue, innerSym, isAsync);

// Pass along the start and end random initialization bits for this register.
if (auto randomRegister = op->getAttr("firrtl.random_init_register"))
if (auto randomRegister = op->getDiscardableAttr("firrtl.random_init_register"))
reg->setAttr("firrtl.random_init_register", randomRegister);
if (auto randomStart = op->getAttr("firrtl.random_init_start"))
if (auto randomStart = op->getDiscardableAttr("firrtl.random_init_start"))
reg->setAttr("firrtl.random_init_start", randomStart);
if (auto randomEnd = op->getAttr("firrtl.random_init_end"))
if (auto randomEnd = op->getDiscardableAttr("firrtl.random_init_end"))
reg->setAttr("firrtl.random_init_end", randomEnd);

// Move SV attributes.
Expand Down Expand Up @@ -3296,7 +3296,7 @@ LogicalResult FIRRTLLowering::visitDecl(InstanceOp oldInstance) {
innerSym.getSymName());
// If the lowered op already had output file information, then use that.
// Otherwise, generate some default bind information.
if (auto outputFile = oldInstance->getAttr("output_file"))
if (auto outputFile = oldInstance->getDiscardableAttr("output_file"))
bindOp->setAttr("output_file", outputFile);
// Add the bind to the circuit state. This will be moved outside of the
// encapsulating module after all modules have been processed in parallel.
Expand Down
10 changes: 5 additions & 5 deletions lib/Dialect/SV/Transforms/SVExtractTestCode.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -545,7 +545,7 @@ static bool isAssertOp(hw::HWSymbolCache &symCache, Operation *op) {
// phase and are not instances that could possibly have extract flags on them.
if (auto inst = dyn_cast<hw::InstanceOp>(op))
if (auto *mod = symCache.getDefinition(inst.getModuleNameAttr()))
if (mod->getAttr("firrtl.extract.assert.extra"))
if (mod->getDiscardableAttr("firrtl.extract.assert.extra"))
return true;

// If the format of assert is "ifElseFatal", PrintOp is lowered into
Expand All @@ -570,7 +570,7 @@ static bool isCoverOp(hw::HWSymbolCache &symCache, Operation *op) {
// phase and are not instances that could possibly have extract flags on them.
if (auto inst = dyn_cast<hw::InstanceOp>(op))
if (auto *mod = symCache.getDefinition(inst.getModuleNameAttr()))
if (mod->getAttr("firrtl.extract.cover.extra"))
if (mod->getDiscardableAttr("firrtl.extract.cover.extra"))
return true;
return isa<CoverOp, CoverConcurrentOp, verif::CoverOp, verif::ClockedCoverOp>(
op);
Expand All @@ -581,7 +581,7 @@ static bool isAssumeOp(hw::HWSymbolCache &symCache, Operation *op) {
// phase and are not instances that could possibly have extract flags on them.
if (auto inst = dyn_cast<hw::InstanceOp>(op))
if (auto *mod = symCache.getDefinition(inst.getModuleNameAttr()))
if (mod->getAttr("firrtl.extract.assume.extra"))
if (mod->getDiscardableAttr("firrtl.extract.assume.extra"))
return true;

return isa<AssumeOp, AssumeConcurrentOp, verif::AssumeOp,
Expand Down Expand Up @@ -787,8 +787,8 @@ void SVExtractTestCodeImplPass::runOnOperation() {
continue;

// In the module is in test harness, we don't have to extract from it.
if (rtlmod->hasAttr("firrtl.extract.do_not_extract")) {
rtlmod->removeAttr("firrtl.extract.do_not_extract");
if (rtlmod->getDiscardableAttr("firrtl.extract.do_not_extract")) {
rtlmod->removeDiscardableAttr("firrtl.extract.do_not_extract");
continue;
}

Expand Down
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