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Automatic merge of 'next' into merge (2024-07-12 22:47)
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@mpe
mpe committed Jul 12, 2024
2 parents 840a696 + 90e812a commit 582b0e5
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Showing 10 changed files with 106 additions and 77 deletions.
18 changes: 0 additions & 18 deletions Documentation/arch/powerpc/cpu_families.rst
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Expand Up @@ -128,24 +128,6 @@ IBM BookE
- All 32 bit::

+--------------+
| 401 |
+--------------+
|
|
v
+--------------+
| 403 |
+--------------+
|
|
v
+--------------+
| 405 |
+--------------+
|
|
v
+--------------+
| 440 |
+--------------+
|
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1 change: 1 addition & 0 deletions Documentation/arch/powerpc/elf_hwcaps.rst
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Expand Up @@ -91,6 +91,7 @@ PPC_FEATURE_HAS_MMU

PPC_FEATURE_HAS_4xxMAC
The processor is 40x or 44x family.
Unused in the kernel since 732b32daef80 ("powerpc: Remove core support for 40x")

PPC_FEATURE_UNIFIED_CACHE
The processor has a unified L1 cache for instructions and data, as
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2 changes: 1 addition & 1 deletion arch/powerpc/boot/wrapper
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Expand Up @@ -337,7 +337,7 @@ ps3)
make_space=n
pie=
;;
ep88xc|ep405|ep8248e)
ep88xc|ep8248e)
platformo="$object/fixed-head.o $object/$platform.o"
binary=y
;;
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3 changes: 1 addition & 2 deletions arch/powerpc/include/asm/cpu_has_feature.h
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Expand Up @@ -24,9 +24,8 @@ static __always_inline bool cpu_has_feature(unsigned long feature)
{
int i;

#ifndef __clang__ /* clang can't cope with this */
BUILD_BUG_ON(!__builtin_constant_p(feature));
#endif
BUILD_BUG_ON(__builtin_popcountl(feature) > 1);

#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG
if (!static_key_feature_checks_initialized) {
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3 changes: 1 addition & 2 deletions arch/powerpc/include/asm/mmu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -239,9 +239,8 @@ static __always_inline bool mmu_has_feature(unsigned long feature)
{
int i;

#ifndef __clang__ /* clang can't cope with this */
BUILD_BUG_ON(!__builtin_constant_p(feature));
#endif
BUILD_BUG_ON(__builtin_popcountl(feature) > 1);

#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG
if (!static_key_feature_checks_initialized) {
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2 changes: 2 additions & 0 deletions arch/powerpc/include/asm/ppc-opcode.h
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Original file line number Diff line number Diff line change
Expand Up @@ -471,6 +471,7 @@
#define PPC_RAW_VCMPEQUB_RC(vrt, vra, vrb) \
(0x10000006 | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | __PPC_RC21)
#define PPC_RAW_LD(r, base, i) (0xe8000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_DS(i))
#define PPC_RAW_LWA(r, base, i) (0xe8000002 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_DS(i))
#define PPC_RAW_LWZ(r, base, i) (0x80000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
#define PPC_RAW_LWZX(t, a, b) (0x7c00002e | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
#define PPC_RAW_STD(r, base, i) (0xf8000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_DS(i))
Expand Down Expand Up @@ -535,6 +536,7 @@
#define PPC_RAW_MULI(d, a, i) (0x1c000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
#define PPC_RAW_DIVW(d, a, b) (0x7c0003d6 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
#define PPC_RAW_DIVWU(d, a, b) (0x7c000396 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
#define PPC_RAW_DIVD(d, a, b) (0x7c0003d2 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
#define PPC_RAW_DIVDU(d, a, b) (0x7c000392 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
#define PPC_RAW_DIVDE(t, a, b) (0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
#define PPC_RAW_DIVDE_DOT(t, a, b) (0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
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118 changes: 88 additions & 30 deletions arch/powerpc/net/bpf_jit_comp64.c
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Original file line number Diff line number Diff line change
Expand Up @@ -510,20 +510,33 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
case BPF_ALU | BPF_DIV | BPF_X: /* (u32) dst /= (u32) src */
case BPF_ALU | BPF_MOD | BPF_X: /* (u32) dst %= (u32) src */
if (BPF_OP(code) == BPF_MOD) {
EMIT(PPC_RAW_DIVWU(tmp1_reg, dst_reg, src_reg));
if (off)
EMIT(PPC_RAW_DIVW(tmp1_reg, dst_reg, src_reg));
else
EMIT(PPC_RAW_DIVWU(tmp1_reg, dst_reg, src_reg));

EMIT(PPC_RAW_MULW(tmp1_reg, src_reg, tmp1_reg));
EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg));
} else
EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, src_reg));
if (off)
EMIT(PPC_RAW_DIVW(dst_reg, dst_reg, src_reg));
else
EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, src_reg));
goto bpf_alu32_trunc;
case BPF_ALU64 | BPF_DIV | BPF_X: /* dst /= src */
case BPF_ALU64 | BPF_MOD | BPF_X: /* dst %= src */
if (BPF_OP(code) == BPF_MOD) {
EMIT(PPC_RAW_DIVDU(tmp1_reg, dst_reg, src_reg));
if (off)
EMIT(PPC_RAW_DIVD(tmp1_reg, dst_reg, src_reg));
else
EMIT(PPC_RAW_DIVDU(tmp1_reg, dst_reg, src_reg));
EMIT(PPC_RAW_MULD(tmp1_reg, src_reg, tmp1_reg));
EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg));
} else
EMIT(PPC_RAW_DIVDU(dst_reg, dst_reg, src_reg));
if (off)
EMIT(PPC_RAW_DIVD(dst_reg, dst_reg, src_reg));
else
EMIT(PPC_RAW_DIVDU(dst_reg, dst_reg, src_reg));
break;
case BPF_ALU | BPF_MOD | BPF_K: /* (u32) dst %= (u32) imm */
case BPF_ALU | BPF_DIV | BPF_K: /* (u32) dst /= (u32) imm */
Expand All @@ -544,19 +557,31 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
switch (BPF_CLASS(code)) {
case BPF_ALU:
if (BPF_OP(code) == BPF_MOD) {
EMIT(PPC_RAW_DIVWU(tmp2_reg, dst_reg, tmp1_reg));
if (off)
EMIT(PPC_RAW_DIVW(tmp2_reg, dst_reg, tmp1_reg));
else
EMIT(PPC_RAW_DIVWU(tmp2_reg, dst_reg, tmp1_reg));
EMIT(PPC_RAW_MULW(tmp1_reg, tmp1_reg, tmp2_reg));
EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg));
} else
EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, tmp1_reg));
if (off)
EMIT(PPC_RAW_DIVW(dst_reg, dst_reg, tmp1_reg));
else
EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, tmp1_reg));
break;
case BPF_ALU64:
if (BPF_OP(code) == BPF_MOD) {
EMIT(PPC_RAW_DIVDU(tmp2_reg, dst_reg, tmp1_reg));
if (off)
EMIT(PPC_RAW_DIVD(tmp2_reg, dst_reg, tmp1_reg));
else
EMIT(PPC_RAW_DIVDU(tmp2_reg, dst_reg, tmp1_reg));
EMIT(PPC_RAW_MULD(tmp1_reg, tmp1_reg, tmp2_reg));
EMIT(PPC_RAW_SUB(dst_reg, dst_reg, tmp1_reg));
} else
EMIT(PPC_RAW_DIVDU(dst_reg, dst_reg, tmp1_reg));
if (off)
EMIT(PPC_RAW_DIVD(dst_reg, dst_reg, tmp1_reg));
else
EMIT(PPC_RAW_DIVDU(dst_reg, dst_reg, tmp1_reg));
break;
}
goto bpf_alu32_trunc;
Expand Down Expand Up @@ -676,8 +701,14 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
/* special mov32 for zext */
EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 0, 0, 31));
break;
}
EMIT(PPC_RAW_MR(dst_reg, src_reg));
} else if (off == 8) {
EMIT(PPC_RAW_EXTSB(dst_reg, src_reg));
} else if (off == 16) {
EMIT(PPC_RAW_EXTSH(dst_reg, src_reg));
} else if (off == 32) {
EMIT(PPC_RAW_EXTSW(dst_reg, src_reg));
} else if (dst_reg != src_reg)
EMIT(PPC_RAW_MR(dst_reg, src_reg));
goto bpf_alu32_trunc;
case BPF_ALU | BPF_MOV | BPF_K: /* (u32) dst = imm */
case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = (s64) imm */
Expand All @@ -699,11 +730,12 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
*/
case BPF_ALU | BPF_END | BPF_FROM_LE:
case BPF_ALU | BPF_END | BPF_FROM_BE:
case BPF_ALU64 | BPF_END | BPF_FROM_LE:
#ifdef __BIG_ENDIAN__
if (BPF_SRC(code) == BPF_FROM_BE)
goto emit_clear;
#else /* !__BIG_ENDIAN__ */
if (BPF_SRC(code) == BPF_FROM_LE)
if (BPF_CLASS(code) == BPF_ALU && BPF_SRC(code) == BPF_FROM_LE)
goto emit_clear;
#endif
switch (imm) {
Expand Down Expand Up @@ -936,13 +968,19 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
*/
/* dst = *(u8 *)(ul) (src + off) */
case BPF_LDX | BPF_MEM | BPF_B:
case BPF_LDX | BPF_MEMSX | BPF_B:
case BPF_LDX | BPF_PROBE_MEM | BPF_B:
case BPF_LDX | BPF_PROBE_MEMSX | BPF_B:
/* dst = *(u16 *)(ul) (src + off) */
case BPF_LDX | BPF_MEM | BPF_H:
case BPF_LDX | BPF_MEMSX | BPF_H:
case BPF_LDX | BPF_PROBE_MEM | BPF_H:
case BPF_LDX | BPF_PROBE_MEMSX | BPF_H:
/* dst = *(u32 *)(ul) (src + off) */
case BPF_LDX | BPF_MEM | BPF_W:
case BPF_LDX | BPF_MEMSX | BPF_W:
case BPF_LDX | BPF_PROBE_MEM | BPF_W:
case BPF_LDX | BPF_PROBE_MEMSX | BPF_W:
/* dst = *(u64 *)(ul) (src + off) */
case BPF_LDX | BPF_MEM | BPF_DW:
case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
Expand All @@ -952,7 +990,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
* load only if addr is kernel address (see is_kernel_addr()), otherwise
* set dst_reg=0 and move on.
*/
if (BPF_MODE(code) == BPF_PROBE_MEM) {
if (BPF_MODE(code) == BPF_PROBE_MEM || BPF_MODE(code) == BPF_PROBE_MEMSX) {
EMIT(PPC_RAW_ADDI(tmp1_reg, src_reg, off));
if (IS_ENABLED(CONFIG_PPC_BOOK3E_64))
PPC_LI64(tmp2_reg, 0x8000000000000000ul);
Expand All @@ -965,30 +1003,47 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
* Check if 'off' is word aligned for BPF_DW, because
* we might generate two instructions.
*/
if (BPF_SIZE(code) == BPF_DW && (off & 3))
if ((BPF_SIZE(code) == BPF_DW ||
(BPF_SIZE(code) == BPF_B && BPF_MODE(code) == BPF_PROBE_MEMSX)) &&
(off & 3))
PPC_JMP((ctx->idx + 3) * 4);
else
PPC_JMP((ctx->idx + 2) * 4);
}

switch (size) {
case BPF_B:
EMIT(PPC_RAW_LBZ(dst_reg, src_reg, off));
break;
case BPF_H:
EMIT(PPC_RAW_LHZ(dst_reg, src_reg, off));
break;
case BPF_W:
EMIT(PPC_RAW_LWZ(dst_reg, src_reg, off));
break;
case BPF_DW:
if (off % 4) {
EMIT(PPC_RAW_LI(tmp1_reg, off));
EMIT(PPC_RAW_LDX(dst_reg, src_reg, tmp1_reg));
} else {
EMIT(PPC_RAW_LD(dst_reg, src_reg, off));
if (BPF_MODE(code) == BPF_MEMSX || BPF_MODE(code) == BPF_PROBE_MEMSX) {
switch (size) {
case BPF_B:
EMIT(PPC_RAW_LBZ(dst_reg, src_reg, off));
EMIT(PPC_RAW_EXTSB(dst_reg, dst_reg));
break;
case BPF_H:
EMIT(PPC_RAW_LHA(dst_reg, src_reg, off));
break;
case BPF_W:
EMIT(PPC_RAW_LWA(dst_reg, src_reg, off));
break;
}
} else {
switch (size) {
case BPF_B:
EMIT(PPC_RAW_LBZ(dst_reg, src_reg, off));
break;
case BPF_H:
EMIT(PPC_RAW_LHZ(dst_reg, src_reg, off));
break;
case BPF_W:
EMIT(PPC_RAW_LWZ(dst_reg, src_reg, off));
break;
case BPF_DW:
if (off % 4) {
EMIT(PPC_RAW_LI(tmp1_reg, off));
EMIT(PPC_RAW_LDX(dst_reg, src_reg, tmp1_reg));
} else {
EMIT(PPC_RAW_LD(dst_reg, src_reg, off));
}
break;
}
break;
}

if (size != BPF_DW && insn_is_zext(&insn[i + 1]))
Expand Down Expand Up @@ -1065,6 +1120,9 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
case BPF_JMP | BPF_JA:
PPC_JMP(addrs[i + 1 + off]);
break;
case BPF_JMP32 | BPF_JA:
PPC_JMP(addrs[i + 1 + imm]);
break;

case BPF_JMP | BPF_JGT | BPF_K:
case BPF_JMP | BPF_JGT | BPF_X:
Expand Down
1 change: 0 additions & 1 deletion arch/powerpc/platforms/Kconfig.cputype
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Original file line number Diff line number Diff line change
Expand Up @@ -250,7 +250,6 @@ config TARGET_CPU
default "e6500" if E6500_CPU
default "power4" if POWERPC64_CPU && !CPU_LITTLE_ENDIAN
default "power8" if POWERPC64_CPU && CPU_LITTLE_ENDIAN
default "405" if 405_CPU
default "440" if 440_CPU
default "464" if 464_CPU
default "476" if 476_CPU
Expand Down
33 changes: 11 additions & 22 deletions arch/powerpc/xmon/ppc-dis.c
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Original file line number Diff line number Diff line change
Expand Up @@ -122,32 +122,21 @@ int print_insn_powerpc (unsigned long insn, unsigned long memaddr)
bool insn_is_short;
ppc_cpu_t dialect;

dialect = PPC_OPCODE_PPC | PPC_OPCODE_COMMON
| PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_ALTIVEC;
dialect = PPC_OPCODE_PPC | PPC_OPCODE_COMMON;

if (cpu_has_feature(CPU_FTRS_POWER5))
dialect |= PPC_OPCODE_POWER5;
if (IS_ENABLED(CONFIG_PPC64))
dialect |= PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_CELL |
PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 |
PPC_OPCODE_POWER9;

if (cpu_has_feature(CPU_FTRS_CELL))
dialect |= (PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC);
if (cpu_has_feature(CPU_FTR_TM))
dialect |= PPC_OPCODE_HTM;

if (cpu_has_feature(CPU_FTRS_POWER6))
dialect |= (PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC);
if (cpu_has_feature(CPU_FTR_ALTIVEC))
dialect |= PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2;

if (cpu_has_feature(CPU_FTRS_POWER7))
dialect |= (PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7
| PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX);

if (cpu_has_feature(CPU_FTRS_POWER8))
dialect |= (PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
| PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX);

if (cpu_has_feature(CPU_FTRS_POWER9))
dialect |= (PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 | PPC_OPCODE_HTM
| PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
| PPC_OPCODE_VSX | PPC_OPCODE_VSX3);
if (cpu_has_feature(CPU_FTR_VSX))
dialect |= PPC_OPCODE_VSX | PPC_OPCODE_VSX3;

/* Get the major opcode of the insn. */
opcode = NULL;
Expand Down
2 changes: 1 addition & 1 deletion drivers/macintosh/therm_windtunnel.c
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Original file line number Diff line number Diff line change
Expand Up @@ -549,7 +549,7 @@ g4fan_exit( void )
platform_driver_unregister( &therm_of_driver );

if( x.of_dev )
of_device_unregister( x.of_dev );
of_platform_device_destroy(&x.of_dev->dev, NULL);
}

module_init(g4fan_init);
Expand Down

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