New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Adds support for aliases. #4

Open

martinhansdk wants to merge 1 commit into ldoolitt:master from martinhansdk:master

martinhansdk commented Oct 2, 2017

Maps the VHDL alias keyword to the Verilog alias keyword.


          Adds support for aliases.

d9096db

Owner

ldoolitt commented Nov 29, 2017

I can believe this addresses your use case. Do you have an example Verilog module that uses alias?
I can't get it to go through iverilog.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet