Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Initial support for string type. #10

Open
wants to merge 1 commit into
base: master
Choose a base branch
from

Conversation

jeinstei
Copy link

@jeinstei jeinstei commented Dec 4, 2017

I think I found all the places this is used. I haven't been able to break it yet, at least.

@jeinstei
Copy link
Author

jeinstei commented Dec 5, 2017

Note that Verilog doesn't really support a string type natively. SystemVerilog does.

@jeinstei
Copy link
Author

jeinstei commented Dec 5, 2017

Here's what I'm getting from the standard:

unconstrained array types are allowed as long as the length can be determined by the actual/initializer. Otherwise it is necessary to have a constraint.

@rodrigomelo9
Copy link
Collaborator

I did not found this sentence in IEEE Std 1076-1993 or IEEE Std 1364-2001. In the last one, the string support is depicted in section 2.6, page 10.

@jeinstei
Copy link
Author

jeinstei commented Dec 6, 2017

I'm find only allowing constrained strings-- but I'm finding Std 1076, 2000 Edition, section 13.7. I think you're correct except for some special, procedure cases. (ie procedure read_file)

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants