PLL

PLL- Need: To generate clk signal with spectral purity which is otherwise difficult to achieve with only VCO(Voltage Controlled Oscillator) or only Quartz crystal.

Parts of PLL block diagram:

• Phase frequency detector: Does the comparison of reference with output signal

  • It has 2 output signals, up signal to increase the frequency and down signal to decrease the frequency of the output signal of PLL

• Charge pump: Converts output of PFD signal to analog signal

  • It gives analog equivalent of up and down signal by either increasing or decreasing the voltage magnitude
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• Low pass filter: Multiple aspects, primarily to smoothen the output signal and also to stabilize the circuit.

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• Voltage controlled oscillator: Generation of clk signal as per the analog signal from charge pump.

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• Frequency divider: Coefficient value of this divider decides the clock multiplier value of PLL. If divider is dividing the output clock by 8 then, PLL can multiply the input signal by 8.

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Specifications:

• Supply voltage: 1.8V
• Temperature: room temperature
• Process corner: TT
• Reference clock signal: Fmin = 5MHz and Fmax = 12.5 MHz
• Duty cycle: 50%
• Multiplier: 8x

Pre-layout simulations:

Frequency divider circuit: Blue signal= input clock Red signal = Output of clk divider

Charge pump circuit:

Graph of output voltage due to current leakage (and when no input is applied):

Graph of output voltage for up signal:

Graph of output voltage for down signal:

Voltage Controlled Circuit:

Phase Frequency Detector circuit:

Final simulation of PLL circuit:

And the zoomed-in version at the end of the waveform where the charge pump output is stable:

In the above image, it can be seen that we are getting the periodic output of up and down signals even when the charge pump output is stable. So, it looks like the PLL is not correctly locked. The reason behind this is unknown. Here, few approaches to allow PLL to be locked are explored.

Two possible approaches were assumed:

• VCO output frequency is not stable
• Input to VCO (Charge pump/loop filter output is fluctuating)

The first option is explored to good extent and is described below.

• Firtly, tried to use ac analysis to plot the frequency domain plot of the output clk signal of VCO but, it was not possible to get the frequency domain plot using ac analysis without an ac source in the design. Then, another approach was to use FFT (Fast Fourier Transform) to get the frequency domain plot and, was getting this output (this graph is the simulation output of VCO only and it's around 28MHz):

The above graph is achieved with following statements in control block:

There are still unanswered questions like why do we have a bump at the start of the graph at 0MHz where there should be no DC at the output.

So, finally got the clock output with the transcient analysis with the complete prelayput simulation of the PLL circuit at different clock samples.

At 800th VCO output clk signal sample:

At 3000th VCO output clk sample:

At 6000th VCO output clk sample:

At 10000th VCO output clk sample:

At 12000th VCO output clk sample:

At 13500th VCO output clk sample (Fref is the frequency of the reference clock signal):

The above measurements are taken with the help of .meas statment in ngspice used in following manner (there is a need of transcient analysis with control block for this to work):

So, the analysis of VCO with different control voltages for above mentioned frequency output:

Sr	Vcontrol input voltage (in volts)	Output clock frequency (in MHz)
1	0.65	63.72
2	0.67	87.48
3	0.68	101.91
4	0.6782	99.18
5	0.679	100.39 (The frequency that we want)
6	0.6925	122.67
7	0.6935	124.5
8	0.6938	124.99 (The frequency that we are getting)
9	0.694	125.5

The voltage difference between required input control voltage and actual control voltage Vdiff = 0.6938 – 0.679 = 14.8 mV

Basically, we are getting 14.8 mV of extra voltage at the output of charge pump which is causing VCO to give output which is 125MHz. This could be related to the process node differences (The PLL specifications were originally planned for 180nm technology node but, the used technology node is 130nm)

Noise analysis:

It was seen that the VCO output is not matching the reference clock input which can be seen below:

The zoomed-in version:

In above image, we can see that, the reference clock signal is not aligned with the VCO clock output signal in the second half of clock cycle. This is achieved by using VCO and PFD (Phase Frequency Detector) circuits only. VCO input was fixed at 0.7V and the output was directly connected to one of the inputs of PFD circuit and another input was connected to reference clock signal. Then, this reference clock signal was manually tuned to match the output frequency of the VCO for 0.7V of control voltage input. This helped in determining the differences in the output of VCO with normal clock signal.

The misalignment was assumed to be due to phase noise that is inherent in VCO designs. To explore whether there is a phase noise in the output of VCO, noise analysis of the ngspice was expolred.

Got these results:

Total output noise in 1Hz to 100MHz range was nearly 800 uV.

This graph shows the output noise spectrum plot:

The zoomed-in version of the same:

However, the output that we see here is the ac small signal noise and not the phase noise as we had expected (this has also been confirmed with the ngspice community as well).

Acknowledgement

• Kunal Ghosh, Co-founder of VLSI System Design
• Darío San Martín Molina, Analog IC designer
• Laxmi S, Student of Hardware Design and Machine Learning
• Google Skywater and Efabless