Add VHDL-2008 version of pipelining package #8
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I thought, this version package could benefit from some VHDL-2008 features,
such as generic types and functions, unresolved numeric types, and definition
of the resolved types as subtypes of the unresolved ones.
I added universal components independent from data ports types, so
they can be used for delaying or pipelining objects of user-defined types
(like records and arrays) without verbose type conversions.
The fixed delay line component in this implementation uses else-generate
clause, so the compiler does not produce false warnings about possible
double assignments to an object of unresolved type like it used to do
in fixed_delay_line_sulv. It does not understand that
STAGES = 0
andSTAGES > 0
are contradictory to each other.Different components for slv and sulv are not necessary in VHDL-2008, thanks
to the new definition of resolved types. However, I left pipeline_slv here
as an alias for
pipeline_sulv
, so the package's interface stays the same.The package uses unresolved_signed and unresolved_unsigned instead of signed
and unsigned.
The package provides an additional definition of the dynamic delay line for
std_ulogic
(dynamic_delay_line
) type for consistency.All components in this package are now just instantiating their universal versions.
It helps to avoid code duplication and makes editing easier. However, I think it
might be better to define each component independently, so they can be copyed
from the package on their own. If it is the case, I can commit a version of the
package with such a code style.