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Add VHDL-2008 version of pipelining package #8

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merged 1 commit into from
Jun 4, 2023

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oswald3141
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I thought, this version package could benefit from some VHDL-2008 features,
such as generic types and functions, unresolved numeric types, and definition
of the resolved types as subtypes of the unresolved ones.

I added universal components independent from data ports types, so
they can be used for delaying or pipelining objects of user-defined types
(like records and arrays) without verbose type conversions.

The fixed delay line component in this implementation uses else-generate
clause, so the compiler does not produce false warnings about possible
double assignments to an object of unresolved type like it used to do
in fixed_delay_line_sulv. It does not understand that STAGES = 0 and
STAGES > 0 are contradictory to each other.

Different components for slv and sulv are not necessary in VHDL-2008, thanks
to the new definition of resolved types. However, I left pipeline_slv here
as an alias for pipeline_sulv, so the package's interface stays the same.

The package uses unresolved_signed and unresolved_unsigned instead of signed
and unsigned.

The package provides an additional definition of the dynamic delay line for
std_ulogic (dynamic_delay_line) type for consistency.

All components in this package are now just instantiating their universal versions.
It helps to avoid code duplication and makes editing easier. However, I think it
might be better to define each component independently, so they can be copyed
from the package on their own. If it is the case, I can commit a version of the
package with such a code style.

Add type independed components, use VHDL-2008 language
constructions where possible.
@oswald3141
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I'm not sure whether asking for a reset function in the universal components is a good idea, Maybe it's better to ask for an empty element? In many cases it won't require the special definition, inline would be fine...

@kevinpt kevinpt merged commit 14bff60 into kevinpt:master Jun 4, 2023
@cweickhmann
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I've written a tapped delay line if that is of any interest...

I don't know if @oswald3141's implementation solves the dependency problem in filtering_2008. And of course my code is green horn level, so I am happy for any feedback.

https://git.gsi.de/c.weickhmann/kevinpt_vhdl-extras/-/blob/master/rtl/extras_2008/pipelining_2008.vhdl

@oswald3141 oswald3141 deleted the pipelining_2008 branch June 26, 2023 13:34
@oswald3141
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Hi @cweickhmann,
No, my version doesn't solve #4, I think it was closed too soon.
I can't fined a definition of tapped_delay_line anywhere in the library. It is only mentioned in the documentation. And, there's no full analog of it in pipelining.
I would argue that a "fully visible" delay line is not such a general purpose component. That is why I don't know if it should be included in pipelining at all. I would just write a separate implementation for it right in filtering. But, of course, I am open for a discussion.

@cweickhmann
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Hi! I know it's not in there, that's why I implemented it. The link above points to my own fork of the library with my code for your consideration.
I'm really new to HDL, so I don't know what's the best or most practical choice.
Looking back, it's a fairly straight-forward thing to write. But coming from the software land, it felt a bit odd it was simply nowhere to be found without any comment.

I ended up writing three versions for different data types. I now doubt they are all necessary.

entity tapped_delay_line is
-- ...
entity tapped_delay_line_signed is
-- ...
entity tapped_delay_line_sfixed is
-- ...

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3 participants