Update pipelining_2008 #14
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"register_balancing" is an ISE synthesis engine (XST) attribute. It is not supported by Vivado, and ISE does not support VHDL-2008. So, the attribute is replaced by a pair of Vivado's ones.
Breaks compatibility! An approach with default element tutned out to be much less wordy than the one with a resetting function. The function, basically, always contains a definition of a default element anyway.
pipeline_* components now allow selecting synchronous or asynchronous reset type.
A generic parameter ATTR_SRL_STYLE is added. The parameter allows one to select a shift register implementation method in Xilinx Vivado.
Breaks compatibility! In most cases, elements initialization is useful. It improves the quality of simulation results. However, it may prevent some optimizations (at least in Vivado). So, this commit adds a generic which controls whether the elements are initialized or not. By default the elements are initialized now.
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This PR contains the following changes:
pipeline_*components. The current version uses the attribute name from ISE, which does not support VHDL 2008. The new version replaces it with the name Vivado supports.pipeline_*components is replaced with a generic constant containing an empty, resetted element. This approach is more convenient and requires less boilerplate (the function, basically, always contains a definition of a default element anyway). This change breaks compatibility with the current version.pipeline_*components now allow to choose between asynchronous and synchronous reset.fixed_delay_line_*components now allow to choose a shift registers implementation style (Xilinx only).fixed_delay_line_*components now allow to initialize the delay line elements. Since generally initialization decreases a chance of a simulation/hardware mismatch, and cases when it prevents optimizations are rare, the initialization is enabled by default. However, it breaks compatibility with the current version.