Prepare L14 flipped note

lectures/flipped/L11.md

@@ -111,6 +111,8 @@ fn main() {
 Discuss about non-blocking, blocking, lock-free, and wait-free. See
 <https://www.justsoftwaresolutions.co.uk/threading/non_blocking_lock_free_and_wait_free.html>
 
+Also, <https://preshing.com/20120612/an-introduction-to-lock-free-programming/>
+
 A quick summary:
 
 - non-blocking/blocking: blocking does not cost CPU time, but non-blocking does

lectures/flipped/L14.md

@@ -1,5 +1,10 @@
 # Lecture 14 — Memory Consistency
 
+## Roadmap
+
+We will talk about compiler reordering, hardware reordering, and memory
+consistency models.
+
 ## Context: reordering, e.g. as done by compilers.
 
 Question: if accessing `thing.y` takes a long time, how can we speed up the
@@ -14,7 +19,8 @@ a = b + c;
 
 ## Hardware reordering
 
-hey look! The compiler can still generate code and we get what we don't expect!
+Hey look! The compiler can still generate code and we get what we don't expect!
+But for now let's say we convince the compiler to emit the following logic.
 
 Question: what are possible final values for `y`?
 
@@ -47,11 +53,13 @@ One definition of something we might want:
 
 ## Memory consistency models
 
-Talk about *memory barrier* or *fence*; mfence, sfence, lfence example.
+Talk about *memory barrier* or *fence*; mfence, sfence, lfence examples (x86
+architecture).
 
 * Acquire / Release
 
-From the [Rustonomicon's page](https://doc.rust-lang.org/nomicon/atomics.html#acquire-release)
+From the [Rustonomicon's
+page](https://doc.rust-lang.org/nomicon/atomics.html#acquire-release)
 
 > When thread A releases a location in memory and then thread B subsequently
 > acquires the same location in memory, causality is established. Every write
@@ -130,6 +138,18 @@ simply a mechanism to propagate a newly written value. The memory consistency
 model is the policy that places the bounds on when the value can be propagated
 to a given processor."
 
+## TODO: build a communication server?
+
+The entire lecture may be wrapped as a game, where students connect to the same
+server to read/write values; the server, however, uses the weird source control
+strategy (see
+[here](https://preshing.com/20120710/memory-barriers-are-like-source-control-operations/)
+to respond the reads/writes. In the end, each student can see the changes in the
+correct order, but other students see them in a different order. Then they can
+inject "fence" to ensure other students see the same order as themselves see it.
+
 # After-action report, plam, 27 Feb 2023
 
-I did a bit of reorg in the above notes. It's still not very flipped. But I kind of did the whole thing, and did not talk about cache coherence. Did not check the runtime between SeqCst and Relaxed.
+I did a bit of reorg in the above notes. It's still not very flipped. But I kind
+of did the whole thing, and did not talk about cache coherence. Did not check
+the runtime between SeqCst and Relaxed.