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feat(TM4C123 and Windows): Adding support for GCC on windows
Adding support for TM4C123 and VSCode Cortex Debug with OpenOCD and ARM GDB Changes to linker script and startup code were needed. Disabling Middlewares was also required, just keeping TivaWare Drivers in place for making the current code compatible with TM4C123. This is a quick and dirty solution, improvements are required.
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Josepablo C
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Nov 3, 2024
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,20 @@ | ||
| { | ||
| "configurations": [ | ||
| { | ||
| "name": "Win32", | ||
| "includePath": [ | ||
| "${workspaceFolder}/**", | ||
| "C:/ti/tivaware_c_series_2_1_4_178/", | ||
| "C:/ti/ccs1281/ccs/tools/compiler/ti-cgt-arm_20.2.7.LTS/include/**" | ||
| ], | ||
| "defines": [ | ||
| "_DEBUG", | ||
| "UNICODE", | ||
| "_UNICODE", | ||
| "PART_TM4C123GH6PM", | ||
| "TARGET_IS_TM4C123_RB1" | ||
| ] | ||
| } | ||
| ], | ||
| "version": 4 | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,6 @@ | ||
| { | ||
| "files.associations": { | ||
| "*.h": "c", | ||
| "*.c": "c" | ||
| } | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,238 @@ | ||
| #include <stdint.h> | ||
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| #if PART_TM4C129XNCZAD | ||
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| void ResetISR(void); | ||
| static void NmiSR(void); | ||
| static void FaultISR(void); | ||
| static void IntDefaultHandler(void); | ||
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| extern int main( int argc, char *argv[] ); | ||
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| extern void xPortPendSVHandler( void ); | ||
| extern void xPortSysTickHandler( void ); | ||
| extern void vPortSVCHandler( void ); | ||
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| extern unsigned long _stack_top; | ||
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| __attribute__ ((section(".isr_vector"))) | ||
| void (* const g_pfnVectors[])(void) = | ||
| { | ||
| (void (*)(void))((unsigned long)&_stack_top), | ||
| // The initial stack pointer | ||
| ResetISR, // The reset handler | ||
| NmiSR, // The NMI handler | ||
| FaultISR, // The hard fault handler | ||
| IntDefaultHandler, // The MPU fault handler | ||
| IntDefaultHandler, // The bus fault handler | ||
| IntDefaultHandler, // The usage fault handler | ||
| 0, // Reserved | ||
| 0, // Reserved | ||
| 0, // Reserved | ||
| 0, // Reserved | ||
| vPortSVCHandler, // SVCall handler | ||
| IntDefaultHandler, // Debug monitor handler | ||
| 0, // Reserved | ||
| xPortPendSVHandler, // The PendSV handler | ||
| xPortSysTickHandler, // The SysTick handler | ||
| IntDefaultHandler, // GPIO Port A | ||
| IntDefaultHandler, // GPIO Port B | ||
| IntDefaultHandler, // GPIO Port C | ||
| IntDefaultHandler, // GPIO Port D | ||
| IntDefaultHandler, // GPIO Port E | ||
| IntDefaultHandler, // UART0 Rx and Tx | ||
| IntDefaultHandler, // UART1 Rx and Tx | ||
| IntDefaultHandler, // SSI0 Rx and Tx | ||
| IntDefaultHandler, // I2C0 Master and Slave | ||
| IntDefaultHandler, // PWM Fault | ||
| IntDefaultHandler, // PWM Generator 0 | ||
| IntDefaultHandler, // PWM Generator 1 | ||
| IntDefaultHandler, // PWM Generator 2 | ||
| IntDefaultHandler, // Quadrature Encoder 0 | ||
| IntDefaultHandler, // ADC Sequence 0 | ||
| IntDefaultHandler, // ADC Sequence 1 | ||
| IntDefaultHandler, // ADC Sequence 2 | ||
| IntDefaultHandler, // ADC Sequence 3 | ||
| IntDefaultHandler, // Watchdog timer | ||
| IntDefaultHandler, // Timer 0 subtimer A | ||
| IntDefaultHandler, // Timer 0 subtimer B | ||
| IntDefaultHandler, // Timer 1 subtimer A | ||
| IntDefaultHandler, // Timer 1 subtimer B | ||
| IntDefaultHandler, // Timer 2 subtimer A | ||
| IntDefaultHandler, // Timer 2 subtimer B | ||
| IntDefaultHandler, // Analog Comparator 0 | ||
| IntDefaultHandler, // Analog Comparator 1 | ||
| IntDefaultHandler, // Analog Comparator 2 | ||
| IntDefaultHandler, // System Control (PLL, OSC, BO) | ||
| IntDefaultHandler, // FLASH Control | ||
| IntDefaultHandler, // GPIO Port F | ||
| IntDefaultHandler, // GPIO Port G | ||
| IntDefaultHandler, // GPIO Port H | ||
| IntDefaultHandler, // UART2 Rx and Tx | ||
| IntDefaultHandler, // SSI1 Rx and Tx | ||
| IntDefaultHandler, // Timer 3 subtimer A | ||
| IntDefaultHandler, // Timer 3 subtimer B | ||
| IntDefaultHandler, // I2C1 Master and Slave | ||
| IntDefaultHandler, // CAN0 | ||
| IntDefaultHandler, // CAN1 | ||
| IntDefaultHandler, // Ethernet | ||
| IntDefaultHandler, // Hibernate | ||
| IntDefaultHandler, // USB0 | ||
| IntDefaultHandler, // PWM Generator 3 | ||
| IntDefaultHandler, // uDMA Software Transfer | ||
| IntDefaultHandler, // uDMA Error | ||
| IntDefaultHandler, // ADC1 Sequence 0 | ||
| IntDefaultHandler, // ADC1 Sequence 1 | ||
| IntDefaultHandler, // ADC1 Sequence 2 | ||
| IntDefaultHandler, // ADC1 Sequence 3 | ||
| IntDefaultHandler, // External Bus Interface 0 | ||
| IntDefaultHandler, // GPIO Port J | ||
| IntDefaultHandler, // GPIO Port K | ||
| IntDefaultHandler, // GPIO Port L | ||
| IntDefaultHandler, // SSI2 Rx and Tx | ||
| IntDefaultHandler, // SSI3 Rx and Tx | ||
| IntDefaultHandler, // UART3 Rx and Tx | ||
| IntDefaultHandler, // UART4 Rx and Tx | ||
| IntDefaultHandler, // UART5 Rx and Tx | ||
| IntDefaultHandler, // UART6 Rx and Tx | ||
| IntDefaultHandler, // UART7 Rx and Tx | ||
| IntDefaultHandler, // I2C2 Master and Slave | ||
| IntDefaultHandler, // I2C3 Master and Slave | ||
| IntDefaultHandler, // Timer 4 subtimer A | ||
| IntDefaultHandler, // Timer 4 subtimer B | ||
| IntDefaultHandler, // Timer 5 subtimer A | ||
| IntDefaultHandler, // Timer 5 subtimer B | ||
| IntDefaultHandler, // FPU | ||
| 0, // Reserved | ||
| 0, // Reserved | ||
| IntDefaultHandler, // I2C4 Master and Slave | ||
| IntDefaultHandler, // I2C5 Master and Slave | ||
| IntDefaultHandler, // GPIO Port M | ||
| IntDefaultHandler, // GPIO Port N | ||
| 0, // Reserved | ||
| IntDefaultHandler, // Tamper | ||
| IntDefaultHandler, // GPIO Port P (Summary or P0) | ||
| IntDefaultHandler, // GPIO Port P1 | ||
| IntDefaultHandler, // GPIO Port P2 | ||
| IntDefaultHandler, // GPIO Port P3 | ||
| IntDefaultHandler, // GPIO Port P4 | ||
| IntDefaultHandler, // GPIO Port P5 | ||
| IntDefaultHandler, // GPIO Port P6 | ||
| IntDefaultHandler, // GPIO Port P7 | ||
| IntDefaultHandler, // GPIO Port Q (Summary or Q0) | ||
| IntDefaultHandler, // GPIO Port Q1 | ||
| IntDefaultHandler, // GPIO Port Q2 | ||
| IntDefaultHandler, // GPIO Port Q3 | ||
| IntDefaultHandler, // GPIO Port Q4 | ||
| IntDefaultHandler, // GPIO Port Q5 | ||
| IntDefaultHandler, // GPIO Port Q6 | ||
| IntDefaultHandler, // GPIO Port Q7 | ||
| IntDefaultHandler, // GPIO Port R | ||
| IntDefaultHandler, // GPIO Port S | ||
| IntDefaultHandler, // SHA/MD5 0 | ||
| IntDefaultHandler, // AES 0 | ||
| IntDefaultHandler, // DES3DES 0 | ||
| IntDefaultHandler, // LCD Controller 0 | ||
| IntDefaultHandler, // Timer 6 subtimer A | ||
| IntDefaultHandler, // Timer 6 subtimer B | ||
| IntDefaultHandler, // Timer 7 subtimer A | ||
| IntDefaultHandler, // Timer 7 subtimer B | ||
| IntDefaultHandler, // I2C6 Master and Slave | ||
| IntDefaultHandler, // I2C7 Master and Slave | ||
| IntDefaultHandler, // HIM Scan Matrix Keyboard 0 | ||
| IntDefaultHandler, // One Wire 0 | ||
| IntDefaultHandler, // HIM PS/2 0 | ||
| IntDefaultHandler, // HIM LED Sequencer 0 | ||
| IntDefaultHandler, // HIM Consumer IR 0 | ||
| IntDefaultHandler, // I2C8 Master and Slave | ||
| IntDefaultHandler, // I2C9 Master and Slave | ||
| IntDefaultHandler // GPIO Port T | ||
| }; | ||
|
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| //***************************************************************************** | ||
| // | ||
| // The following are constructs created by the linker, indicating where the | ||
| // the "data" and "bss" segments reside in memory. The initializers for the | ||
| // for the "data" segment resides immediately following the "text" segment. | ||
| // | ||
| //***************************************************************************** | ||
| extern unsigned long _text; | ||
| extern unsigned long _etext; | ||
| extern unsigned long _data; | ||
| extern unsigned long _edata; | ||
| extern unsigned long _bss; | ||
| extern unsigned long _ebss; | ||
|
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| //***************************************************************************** | ||
| // | ||
| // This is the code that gets called when the processor first starts execution | ||
| // following a reset event. Only the absolutely necessary set is performed, | ||
| // after which the application supplied entry() routine is called. Any fancy | ||
| // actions (such as making decisions based on the reset cause register, and | ||
| // resetting the bits in that register) are left solely in the hands of the | ||
| // application. | ||
| // | ||
| //***************************************************************************** | ||
|
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| void ResetISR(void) | ||
| { | ||
|
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| unsigned long *pulSrc, *pulDest; | ||
| pulSrc = &_etext; | ||
| for(pulDest = &_data; pulDest < &_edata; ) | ||
| { | ||
| *pulDest++ = *pulSrc++; | ||
| } | ||
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| for(pulDest = &_bss; pulDest < &_ebss; ) | ||
| { | ||
| *pulDest++ = 0; | ||
| } | ||
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| main( 0x00U , 0x00U ); | ||
| } | ||
|
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| //***************************************************************************** | ||
| // | ||
| // This is the code that gets called when the processor receives a NMI. This | ||
| // simply enters an infinite loop, preserving the system state for examination | ||
| // by a debugger. | ||
| // | ||
| //***************************************************************************** | ||
| static void NmiSR(void) | ||
| { | ||
| while(1) | ||
| { | ||
| } | ||
| } | ||
|
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| //***************************************************************************** | ||
| // | ||
| // This is the code that gets called when the processor receives a fault | ||
| // interrupt. This simply enters an infinite loop, preserving the system state | ||
| // for examination by a debugger. | ||
| // | ||
| //***************************************************************************** | ||
| static void FaultISR(void) | ||
| { | ||
| while(1) | ||
| { | ||
| } | ||
| } | ||
|
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| //***************************************************************************** | ||
| // | ||
| // This is the code that gets called when the processor receives an unexpected | ||
| // interrupt. This simply enters an infinite loop, preserving the system state | ||
| // for examination by a debugger. | ||
| // | ||
| //***************************************************************************** | ||
| static void IntDefaultHandler(void) | ||
| { | ||
| while(1) | ||
| { | ||
| } | ||
| } | ||
|
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||
|
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| #endif |
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