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Merge commit 'dfab93ae929230ec778d6f953117fcaee85f5ea0'
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jingri committed Sep 26, 2015
2 parents a766d47 + dfab93a commit 4531604
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Showing 8 changed files with 336 additions and 21 deletions.
55 changes: 54 additions & 1 deletion arch/arm/include/asm/arch-s3c64xx/s3c6410.h
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Original file line number Diff line number Diff line change
Expand Up @@ -574,7 +574,15 @@
#define NFMECC1_OFFSET 0x38
#define NFSECC_OFFSET 0x3c
#define NFMLCBITPT_OFFSET 0x40

#define NF8ECCERR0_OFFSET 0x44
#define NF8ECCERR1_OFFSET 0x48
#define NF8ECCERR2_OFFSET 0x4c
#define NFM8ECC0_OFFSET 0x50
#define NFM8ECC1_OFFSET 0x54
#define NFM8ECC2_OFFSET 0x58
#define NFM8ECC3_OFFSET 0x5c
#define NFMLC8BITPT0_OFFSET 0x60
#define NFMLC8BITPT1_OFFSET 0x64
#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET)
#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET)
#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET)
Expand All @@ -592,6 +600,15 @@
#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET)
#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET)
#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
#define NF8ECCERR0 (ELFIN_NAND_BASE + NF8ECCERR0_OFFSET)
#define NF8ECCERR1 (ELFIN_NAND_BASE + NF8ECCERR1_OFFSET)
#define NF8ECCERR2 (ELFIN_NAND_BASE + NF8ECCERR2_OFFSET)
#define NFM8ECC0 (ELFIN_NAND_BASE + NFM8ECC0_OFFSET)
#define NFM8ECC1 (ELFIN_NAND_BASE + NFM8ECC1_OFFSET)
#define NFM8ECC2 (ELFIN_NAND_BASE + NFM8ECC2_OFFSET)
#define NFM8ECC3 (ELFIN_NAND_BASE + NFM8ECC3_OFFSET)
#define NFMLC8BITPT0 (ELFIN_NAND_BASE + NFMLC8BITPT0_OFFSET)
#define NFMLC8BITPT1 (ELFIN_NAND_BASE + NFMLC8BITPT0_OFFSET)

#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET)
#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET)
Expand All @@ -611,6 +628,15 @@
#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET)
#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET)
#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
#define NF8ECCERR0_REG __REG(ELFIN_NAND_BASE + NF8ECCERR0_OFFSET)
#define NF8ECCERR1_REG __REG(ELFIN_NAND_BASE + NF8ECCERR1_OFFSET)
#define NF8ECCERR2_REG __REG(ELFIN_NAND_BASE + NF8ECCERR2_OFFSET)
#define NFM8ECC0_REG __REG(ELFIN_NAND_BASE + NFM8ECC0_OFFSET)
#define NFM8ECC1_REG __REG(ELFIN_NAND_BASE + NFM8ECC1_OFFSET)
#define NFM8ECC2_REG __REG(ELFIN_NAND_BASE + NFM8ECC2_OFFSET)
#define NFM8ECC3_REG __REG(ELFIN_NAND_BASE + NFM8ECC3_OFFSET)
#define NFMLC8BITPT0_REG __REG(ELFIN_NAND_BASE + NFMLC8BITPT0_OFFSET)
#define NFMLC8BITPT1_REG __REG(ELFIN_NAND_BASE + NFMLC8BITPT0_OFFSET)

#define NFCONF_ECC_4BIT (1<<24)

Expand Down Expand Up @@ -718,6 +744,32 @@
*/
#define ELFIN_TIMER_BASE 0x7F006000

#define TCFG0_REG __REG(0x7F006000)
#define ULCON1_REG __REG(0x7F005400)
#define UCON1_REG __REG(0x7F005404)
#define UFCON1_REG __REG(0x7F005408)
#define UMCON1_REG __REG(0x7F00540C)
#define UTRSTAT1_REG __REG(0x7F005410)
#define UERSTAT1_REG __REG(0x7F005414)
#define UFSTAT1_REG __REG(0x7F005418)
#define UMSTAT1_REG __REG(0x7F00541c)
#define UTXH1_REG __REG(0x7F005420)
#define URXH1_REG __REG(0x7F005424)
#define UBRDIV1_REG __REG(0x7F005428)
#define UDIVSLOT1_REG __REG(0x7F00542c)
#define UINTP1_REG __REG(0x7F005430)
#define UINTSP1_REG __REG(0x7F005434)
#define UINTM1_REG __REG(0x7F005438)

#define UTRSTAT_TX_EMPTY (1 << 2)
#define UTRSTAT_RX_READY (1 << 0)
#define UART_ERR_MASK 0xF

/*
* PWM timer
*/
#define ELFIN_TIMER_BASE 0x7F006000

#define TCFG0_REG __REG(0x7F006000)
#define TCFG1_REG __REG(0x7F006004)
#define TCON_REG __REG(0x7F006008)
Expand Down Expand Up @@ -894,3 +946,4 @@ static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr)
#endif

#endif /*__S3C6410_H__*/

11 changes: 11 additions & 0 deletions arch/arm/lib/crt0.S
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Original file line number Diff line number Diff line change
Expand Up @@ -103,6 +103,17 @@ _main: /*call by start.S*/
#if defined(CONFIG_NAND_SPL)
/* deprecated, use instead CONFIG_SPL_BUILD */
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) /*0x0c002000 smdk6410.h*/

// ldr r0, = __bss_start /* this is auto-relocated! */
// ldr r1, =__bss_end__ /* this is auto-relocated! */

// mov r2, #0x00000000 /* prepare zero to clear BSS */
//bss_clean:cmp r0, r1 /* while not at end of BSS */
// strlo r2, [r0] /* clear 32-bit BSS word */
// addlo r0, r0, #4 /* move to next */
// blo bss_clean
ldr pc, = nand_boot

#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr sp, =(CONFIG_SPL_STACK)
#else
Expand Down
6 changes: 3 additions & 3 deletions board/samsung/smdk6410/lowlevel_init.S
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Original file line number Diff line number Diff line change
Expand Up @@ -59,7 +59,7 @@ lowlevel_init: /*call by start.S*/
ldr r1, =0x00000555
str r1, [r0, #GPMPUD_OFFSET]
/* all of LEDs are power on*/
ldr r1, =0x000f
ldr r1, =0x0005
str r1, [r0, #GPMDAT_OFFSET]
/*关闭看门狗*/
/* Disable Watchdog, write 0 to 0x7e004000*/
Expand Down Expand Up @@ -274,8 +274,8 @@ uart_asm_init:
nand_asm_init:
ldr r0, =ELFIN_NAND_BASE
ldr r1, [r0, #NFCONF_OFFSET]
orr r1, r1, #0x70
orr r1, r1, #0x7700
orr r1, r1, #0x1 /*TWRPH1 = 0*/
orr r1, r1, #0x1300 /*TWRPH0 = 2, TACLS = 0*/
str r1, [r0, #NFCONF_OFFSET]

ldr r1, [r0, #NFCONT_OFFSET]
Expand Down
18 changes: 18 additions & 0 deletions common/cmd_nand.c
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Original file line number Diff line number Diff line change
Expand Up @@ -659,13 +659,31 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
(u_char *)addr,
WITH_DROP_FFS);
#endif
}else if((!read) && (s != NULL) && (!strcmp(s, ".uboot")) && nand->writesize == 4096){
rwsize = 4096;
nand_write(nand, off, &rwsize, (u_char *)addr);
off+= 4096;
addr+= 2048;
nand_write(nand, off, &rwsize, (u_char *)addr);
off+= 4096;
addr+= 2048;
nand_write(nand, off, &rwsize, (u_char *)addr);
off+= 4096;
addr+= 2048;
nand_write(nand, off, &rwsize, (u_char *)addr);
off+= 4096;
addr+= 2048;
rwsize = CONFIG_SYS_NAND_U_BOOT_SIZE - 8*1024;
ret = nand_write(nand, off, &rwsize, (u_char *)addr);
#ifdef CONFIG_CMD_NAND_YAFFS
} else if (!strcmp(s, ".yaffs")) {
if (read) {
printf("Unknown nand command suffix '%s'.\n", s);
return 1;
}
ret = nand_write_skip_bad(nand, off, &rwsize,

q
(u_char *)addr,
WITH_INLINE_OOB);
#endif
Expand Down
3 changes: 2 additions & 1 deletion drivers/mtd/nand/nand_ids.c
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Original file line number Diff line number Diff line change
Expand Up @@ -112,7 +112,8 @@ const struct nand_flash_dev nand_flash_ids[] = {

/* 16 Gigabit */
{"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
{"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
// {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
{"NAND 2GiB 3,3V 8-bit", 0xD5, 4096, 2048, 4096*128, LP_OPTIONS},
{"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
{"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},

Expand Down
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