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itsvic-dev committed May 2, 2024
1 parent f13bef7 commit 6f1026b
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8 changes: 8 additions & 0 deletions .lcovrc
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# lcov and genhtml configuration
# See http://ltp.sourceforge.net/coverage/lcov/lcovrc.5.php

# Always enable branch coverage
lcov_branch_coverage = 1

# Exclude assertions
lcov_excl_br_line = LCOV_EXCL_BR_LINE|assert|STATUS_ASSERT
13 changes: 13 additions & 0 deletions tests/instructions/shift/asl-a-80.cpp
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#include "testMain.h"
#include "v6502/cpu.h"
#include <cassert>

TEST {
cpu->a = 0x80;
cpu->bus->write(0, 0x0a); // ASL A
cpu->reset();
cpu->executeStep();

assert(cpu->a == 0);
STATUS_ASSERT(STATUS_ZERO | STATUS_CARRY);
}
13 changes: 13 additions & 0 deletions tests/instructions/shift/rol-sec.cpp
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#include "testMain.h"
#include "v6502/cpu.h"
#include <cassert>

TEST {
cpu->bus->write(0, 0x2A); // ROL A
cpu->reset();
cpu->setFlags(STATUS_CARRY);
cpu->executeStep();

assert(cpu->a == 1);
STATUS_ASSERT(0);
}
3 changes: 3 additions & 0 deletions tests/meson.build
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Expand Up @@ -21,6 +21,9 @@ tests = {
'instructions(arith) - SBC #$01 with A=$02': 'instructions/arith/sbc-1-02.cpp',
'instructions(arith) - SBC #$01 with A=$80': 'instructions/arith/sbc-1-80.cpp',

'instructions(shift) - ASL A with A=$80': 'instructions/shift/asl-a-80.cpp',
'instructions(shift) - ROL A with set carry': 'instructions/shift/rol-sec.cpp',

# old bugs
'old bugs - does CMP #$3A with A=$3A work correctly?': 'bugs/cmp_immediate_3a_works.cpp',
}
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