Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface.
Another way to perform timing analysis is to use dynamic simulation, which determines the full behavior of the circuit for a given set of input stimulus vectors. Compared to dynamic simulation, static timing analysis is much faster because it is not necessary to simulate the logical operation of the circuit. STA is also more thorough because it checks all timing paths, not just the logical conditions that are sensitized by a set of test vectors. However, STA can only check the timing, not the functionality, of a circuit design.
When performing timing analysis, STA first breaks down the design into timing paths. Each timing path consists of the following elements:
Startpoint The start of a timing path where data is launched by a clock edge or where the data must be available at a specific time. Every startpoint must be either an input port or a register clock pin.
Combinational logic network Elements that have no memory or internal state. Combinational logic can contain AND, OR, XOR, and inverter elements, but cannot contain flip-flops, latches, registers, or RAM.
Endpoint The end of a timing path where data is captured by a clock edge or where the data must be available at a specific time. Every endpoint must be either a register data input pin or an output port.
Input port to D pin of Lauch Flop.
Clock port of capture flop to Output port
Clock port of lauch flop to D pin of Capture flop
Input port to Output port
These are valid paths to caluculate timing
The time required by a signal to travel form start point to the end point is called Arrival time Arival time is caluculated at end points.
Required time is expected time of signal arival
let arival time is 3.5ns
Max difference (max slack)= 0.8ns =>setup slack, setup timing, setup analysis
(Setup slack = Expected time max - Arrival time)
Min difference (min slack)=-0.1ns =>hold slack, hold timing, hold analysis
(Hold slack = Arrival time - Expected time min)
Types of setup/hold analysis
- reg2reg
- in2reg
- reg2out
- in2out
- clock gating
- recovery/removal
- data-to-data
- latch (time borrow/time given)
Slew/Transition analysis
- Data (max/min) CLK
- Clock (max/min)
Load analysis
- Fanout (max/min)
- Capacitance (max/min)
Clock analysis
- Skew
- Pulse width
Cat 2,3,4 belongs to IO timing
Clock coming to capture flop is coming throgh an and gate. we are trying gate the clock. this thechnique is called clock gateing. This is used to reduce the chip power. if that portion of circuit is not using we can turn of clock which imples flop dosent switches.
For flops we have asynchronous pins also present.
Now the combination logic that connected to reset pin is replaced by and gate, this is done to save some power in reset path. if control is high, the gate is open.
And control signal should be in sync.to get them into synchronous level, so we take a and ctrl as final points to analise the ariving time.
latch is level triggered. if previos flop to latch dosent met timing constraints, it can barrow some time from level triggerd latch. similarly flop connected at output of latch failted to meet timing constraints, latch can give time to lext flop. thats why latches are very important in design.
There is some minium and maximum requirement of slew. slew and the transition analysis ensures that each and every point on this particular set of it meets that criteria.
Basically if you the slew is too sharp, it will increase short circuit power and if it is too large then it will increase opening time for gate.
Slew analysis has two parts i.e. data and clock
data dosent switch so often as compared to clock. clock has to switch at equal intervels, that that's why the clock transition requirements becomes a bit stringent compared to the data requirements.
fanout analysis- eg. if fanout is 3 whether it is able to charge that load or not.
Capacitance
now among A1 and A2 which we have to consider? that depends on type of analysis that we are doing. lower value considered if we are doing hold analysis, higher value while while doing setup analysis. not lets go with setup time.
AAT-addition. RAT subtraction. RAT defined at destination and from that we go back every node by subtracting delays to find their respective RAT, so that we can find out what causing negative slack. based on that we modify that node. that is called as Engineering Change Order(ECO).
for setup analysis we take the lowest and for( hold we take the highest RAT)
if delay of d(2) is 2-0.35 i.e d(1.65)(diif cell of same fun) the slack would be zero. that is Engineering change order ECO.
at A0 also we can reduce delay by connecting a lunch flop for lower delay.
GBA is Wrost case analysis (take all the wrost case paths) PBA take real path/ actual path that will be traced on sillicon.
Path based analysis is more realistic than graph based analysis. Lets go for PBA.
Lanch flop gets clock after 2 buffer delays and capture flop gets clock after 3 buffer delays
Setup Time is the time before rising edge of CLK, that input D become valid i.e. 'D' input has to be stable such that Qm is sent out, to Q reliably
Input 'D' takes at least 3 inverter delays (Inv1, Inv3 and Inv5/Inv2) + 1 transmission gate delay (Tr1) to become stable before rising edge of CLK
Setup Time = 3 Inverter delay + 1 Transmission gate delay
CIk-Q delay is the time needed to propagate 'Qm' to 'Q'. Note, that 'D' (or 'Qm' from low 'CLK') was stable till output of 'Inv5'. So the time required, to propagate is 1 Clk-Q = transmission gate delay(tr4) + 1 inverter delay(inv6)
Hold Time is the time for which 'D' input remain valid after clock edge. In this case, 'Tr1' is OFF after rising 'CLK'. So, 'D' is allowed to change OR can change, immediately after rise 'CLK' edge. So Hold time is 'zero'
Hence finite Time 'S' required (before clk edge) for 'D' to reach QM i.e. internal delay of Mux1 = Setup time
Clock edge dosent come exactly. Practically, there is a window in which the edge arives.
Reason for having Clock window is clock network in which we have lot of gates that results in variations in clock. Each and Every buffer on sillicon is diffarent.
It is done in foundry
ideal clock operates at 0 and 1. but practically, there might be voltage droop and ground bounce. this cause variations in clock levels
There is a temporary variation in clock period due to jitter
SU-Setup Uncertanity
Since there is only one edge jitter value of hold is less compared to setup(2 edges).
Sources of Variation : Etching Process Variation
Etching process defines the structures in layout (metal,diff..)(rectangle)
Overlap area is diffarent.
it is variation in one inverter. In chain of inverters lot more changes
Gates in middle have some kind of variation as they connected to inverters only inverters at ends may have another variation as they connected to flops.
Sources of Variation : Oxide Thickness
Middle invs have slighntly lower variations
R is not constant, but varies of Id
If these series of inverters are designed to have 100ps delay, it might end up having 101ps,102ps,99ps etc.
OCV on setup timing analysis any of flowing combination DRT +20% +20% -20% -20% DAT +20% -20% +20% -20%
if are reducing by 20%(i.e.-20%) that is CLock Pull-in (we are reducing delay of every cell in clock path)
if are increasing by 20%(i.e.+20%) that is CLock Pull-out (we are increasing delay of every cell in clock path)
this will give more realistic and conservative approch. Clock pull in for DRT and Clock pull out for DAT
in DRT lets delete old numbers and keep new numbers
The Launch clock section and capture clock section highlighted part is common
A cell is showing 2 diffarent delays which is practically not possible.
At a time instant (say 't'), the delay of cell 'b1' can be either 0.043ns or 0.0344ns
So there is an additional pessimism of |0.043ns - 0.0344ns| = 0.0086ns We need to remove this Pessimism
we can Add Additional Pessimium to DRT or subtract from DAT.
Now lets do this on hold timing
we can remove Additional pessimissum from DRT or add to DAT
these concepts will be same for these also
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We summarized rer2reg timing analysis. The concepts we learned for reg2reg analysis can be applied to any other setup/hold analysis.
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While doing Slew/Transition analysis we will be using library setup and hold time.
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Clock analysis is highly dependent on on-chip variation and pessimism removal.
make sure you have atleast
- GNU C++ Compiler v7.3 with -std=c++1z
- Clang C++ Compiler v6.0 with -std=c++17 to check
$ gcc --version
$ clang --version
install cmake with following command
$ sudo apt install cmake
To install Opentimer
$ git clone https://github.com/OpenTimer/OpenTimer.git
$ cd OpenTimer
$ mkdir build
$ cd build
$ cmake ../
$ sudo make
to test
$ make test
in opentimer directory, use the following command to invoke open timer.
$ ./bin/ot-shell
____ _______
/ __ \___ ___ ___/_ __(_)_ _ ___ ____
/ /_/ / _ \/ -_) _ \/ / / / ' \/ -_) __/
\____/ .__/\__/_//_/_/ /_/_/_/_/\__/_/ v2.1.0
/_/
MIT License: type "license" to see more details.
For help, type "help".
For bug reports, issues, and manual, please see:
<https://github.com/OpenTimer/OpenTimer>.
to know commands
ot> help
Exploring Example:
Nishit Chechani
Kunal Ghosh
Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.
Nishit Dinesh Chechani, Postgraduate Student, International Institute of Information Technology, Bangalore
E-Mail: [email protected]
Kunal Ghosh, Director, VSD Corp. Pvt. Ltd
E-Mail: [email protected]