Update DESCRIPTION

[shajoezhu]

kick off ci test on main for rtables, rlistings, formatter and tern

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CLA Assistant Lite bot ✅ All contributors have signed the CLA

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Unit Tests Summary

  1 files   55 suites   2m 54s ⏱️
250 tests 179 ✅  71 💤 0 ❌
491 runs  315 ✅ 176 💤 0 ❌

Results for commit 989c36e.

♻️ This comment has been updated with latest results.

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Code Coverage Summary

Filename                     Stmts    Miss  Cover    Missing
-------------------------  -------  ------  -------  ------------------------------------------------------------------------------
R/ael01_nollt.R                 10       2  80.00%   55-57
R/ael02.R                       27       0  100.00%
R/ael03.R                       34       0  100.00%
R/aet01_aesi.R                 148       1  99.32%   214
R/aet01.R                       98       1  98.98%   172
R/aet02.R                       44       0  100.00%
R/aet03.R                       76       0  100.00%
R/aet04.R                       88       0  100.00%
R/aet05_all.R                   11       0  100.00%
R/aet05.R                       44       1  97.73%   116
R/aet10.R                       42       0  100.00%
R/assertions.R                  93       7  92.47%   11-16, 123
R/cfbt01.R                     107       0  100.00%
R/checks.R                      14       0  100.00%
R/chevron_tlg-S4class.R         24       0  100.00%
R/chevron_tlg-S4methods.R      149       0  100.00%
R/cmt01a.R                      52       0  100.00%
R/coxt01.R                      49       1  97.96%   130
R/dmt01.R                       38       0  100.00%
R/dst01.R                       94       0  100.00%
R/dtht01.R                     102       6  94.12%   51, 55-59
R/egt02.R                       35       0  100.00%
R/egt03.R                       80       1  98.75%   157
R/egt05_qtcat.R                 78       0  100.00%
R/ext01.R                       59       1  98.31%   51
R/fstg01.R                      43       0  100.00%
R/fstg02.R                      48       0  100.00%
R/kmg01.R                       35       6  82.86%   35-40
R/lbt04.R                       90       0  100.00%
R/lbt05.R                       66       5  92.42%   124-129
R/lbt06.R                       70       3  95.71%   141-144
R/lbt07.R                       93       0  100.00%
R/lbt14.R                       63       0  100.00%
R/lbt15.R                       20       0  100.00%
R/mht01.R                       55       0  100.00%
R/mng01.R                       81       7  91.36%   83, 87-91, 153
R/pdt01.R                       60       0  100.00%
R/pdt02.R                       68       0  100.00%
R/rmpt01.R                      59      11  81.36%   88-97, 132
R/rmpt06.R                     134       3  97.76%   210-213
R/rspt01.R                      73       3  95.89%   156-159
R/rtables_utils.R              325      23  92.92%   51, 68, 119, 243, 264, 409-416, 483, 498-500, 502, 571-577, 587, 608
R/standard_rules.R              13       0  100.00%
R/ttet01.R                     120       3  97.50%   202-205
R/utils.R                      182      25  86.26%   144, 160, 179-181, 298-301, 305-308, 335, 339, 351, 353, 365, 382-384, 406-419
R/vst02.R                       45       1  97.78%   109
R/zzz.R                          1       1  0.00%    2
TOTAL                         3340     112  96.65%

Diff against main

Filename                     Stmts    Miss  Cover
-------------------------  -------  ------  --------
R/ael01_nollt.R                -11      +1  -15.24%
R/ael02.R                      +27       0  +100.00%
R/ael03.R                      +34       0  +100.00%
R/aet01_aesi.R                  -2       0  -0.01%
R/aet01.R                       +4       0  +0.04%
R/aet02.R                       -6       0  +100.00%
R/aet03.R                       -1       0  +100.00%
R/aet04.R                       -1       0  +100.00%
R/aet05.R                       +4       0  +0.23%
R/aet10.R                       -1       0  +100.00%
R/assertions.R                  -6      +1  -1.47%
R/chevron_tlg-S4class.R         +6       0  +100.00%
R/chevron_tlg-S4methods.R      +13      -4  +2.94%
R/cmt01a.R                      -6      -6  +10.34%
R/coxt01.R                      +1       0  +0.04%
R/dmt01.R                       +9       0  +100.00%
R/dst01.R                       -1       0  +100.00%
R/dtht01.R                      -1       0  -0.06%
R/egt02.R                       -2       0  +100.00%
R/egt03.R                       +3       0  +0.05%
R/egt05_qtcat.R                 -1       0  +100.00%
R/ext01.R                       -1       0  -0.03%
R/fstg01.R                      -7       0  +100.00%
R/fstg02.R                      -7       0  +100.00%
R/kmg01.R                       +6      +6  -17.14%
R/lbt04.R                       -1       0  +100.00%
R/lbt05.R                       -1       0  -0.11%
R/lbt06.R                       -2       0  -0.12%
R/lbt07.R                       -1       0  +100.00%
R/lbt14.R                       -3       0  +100.00%
R/mht01.R                      -16       0  +100.00%
R/mng01.R                      -15      +6  -7.60%
R/pdt02.R                       -1       0  +100.00%
R/rmpt01.R                      -6       0  -1.72%
R/rmpt06.R                    +134      +3  +97.76%
R/rtables_utils.R              +25      +4  -0.74%
R/standard_rules.R              +2       0  +100.00%
R/ttet01.R                      +3       0  +0.06%
R/utils.R                      +98     +25  -13.74%
R/vst02.R                       -1       0  -0.05%
R/zzz.R                         +1      +1  +100.00%
TOTAL                         +269     +37  -0.91%

Results for commit: 989c36e

Minimum allowed coverage is 80%

♻️ This comment has been updated with latest results

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Unit Test Performance Difference

Test Suite	$Status$	Time on main	$±Time$	$±Tests$	$±Skipped$	$±Failures$	$±Errors$
fstg02	💔	$8.29$	$+1.03$	$0$	$0$	$0$	$0$

Results for commit d434095

♻️ This comment has been updated with latest results.

[shajoezhu]

I have read the CLA Document and I hereby sign the CLA