Architecture updater (auto-sync) - Updating AArch64 (capstone-engine#…

…2026)

* Update sysop inc file

* Fix missing  braces warning

* Handle new system operands

* Fix build errors by renaming.

* Fix segfault

* Fix segfault

* Add custom MCOperand valiadtors

* Add AArch64 case for getFeatureBits

* Fix infinite loop

* Fix braces warning.

* Implement loopuo by name for sys operands

* Fix incorrect translation which remove else if statements.

* Fix several segfaults

* Rename GetRegFromClass patch

* Fix segfaults and asserts

* Fix segfault

* Move MRI setting to Mapping

* Remove unused code

* Add add_op_X functinos for AArch64.

* Add fill detail functins

* Handle RegWithShiftExtend operands

* Handle TypedVectorList operands.

* Handle ComplexRoatation operands

* Handle MemExtend operands

* Handle ImmRangeScale operands

* Handle ExactFPImm operands

* Handle GPRSeqPairsClass operands

* Handle Imm8OptLsl operands

* Handle ImmScale operands

* Handle LogicalImm operands

* Handle Matrix operands

* Handle SME Matrix tiles and vectors.

* Handle normal operands.

* Fix segfault.

* Handle PostInc operands.

* Reorder VecLayout enum to have no duplicate enum value.

* Handle PredicateAsCounter operands

* Handle ZPRasFPR operands

* Handle VectorIndex operands

* Handle UImm12Offset operands.

* Move reg suffix to enum val to single function.

* Handle SVERegOp operands

* Handle SVELogicalImm operands

* Handle SImm operand

* Handle PrefetchOp operands

* Handle Imm and ImmHex operands

* Handle GPR64as32 and GPR64x8 operands

* Add missing break

* Handle FPImm operand

* Handle ExtendedRegister opreand

* Handle CondCode operands

* Handle BTIHintOp operands

* Handle BarrierOption operands

* Handle BarrierXSOption

* Add not implemeted case again

* Handle ArithExtend operands

* Handle AdrpLabel and AlignedLabel operands

* Handle AMNoIndex operands

* Handle AddSubImm operands

* Handle MSRSystemRegisters and MRSSystemRegister operands

* Handle PSBHntOp and RPRFMOperand operands

* Remove unused variables

* Handle InverseCondCode operands

* Handle ImplicityTypedVectorList operands

* Handle ShiftedRegister operands

* Handle Shifter operands

* Handle SIMDType10Operand operands

* Handle SVCROp operands

* Handle SVEPattern operands

* Handle SVEVecLenSpecifier operands

* Handle SysCROperands

* Handle SysXzrPair operands

* Handle PState operands

* Handle VRegOperands

* Primt SME oeprands.

* Fix cs_operand.h include

* Rename arm64 -> aarch64 in python bindings.

* Add Python bindings for SH

* Fix ARM Python bindings (capstone-engine#2127)

* Restructure auto-sync update scripts.

* Move Helper functions to Updater dir

* Move requirements.txt

* Add basic ASUpdater.py

* Run black.

* Add inc file generater to updater

* Add option to select certain inc files fore generation.

* Enable clean build and implement patcher for inc files.

* Format config

* Patch main header files after inc generation.

* Implement clang-format function (unused yet, because it takes forever.)

* Copy generated inc files to arch dir

* Invert clean option (noramlly we need to clean the build dir.)

* Clearify arg doc

* Rename SystemRegister file for AArch64

* Centralize handling of path variables.

* Check if SystemOperands had to be generated before renaming on of its files.

* Replace class parameters by calling get_path

* Remove updater config which only contained paths.

* Add refactor option.

* Remove more path handling in the Configurator.

* Add translation step to updater.

* Fix includes after CppTranslator was moved into the Updater

* Remove updater config

* Fix several issue in the Configurator

* Fix file operations

* Remove addition argument from translator.

* Add Differ step to updater.

* Add path variable for arch_config

* Add diff step.

* Fix typo

* Introduce .clang-format path variable.

* Remove duplicate functions

* Add option to select update steps to execute.

* Check in write functions for write flag.

* Rename PatchMainHeader -> HeaderPatcher

* Move .gitignore

* Add README to vendor dir.

* Add all system operands to cstool output

* Update cstest with aarch64 changes

* Remove wb flag of aarch64 detail struct

* Set updates_flag after decoding

* Set writeback after decoding.

* Rename ARM64 -> AArch64

* Update printer and op mapping

* Exit normally

* Add AArch64 alias

* Fix some tmeplate function calls

* Fix flag check after rebase.

* Fix build by commentig unnused code.

* Add memory operand flag

* Handle memory operands printed via generic printOperand function.

* Handle UImm memory offsets

* Introduce MEM_REG and MEM_IMM op types

* Handle scaled memory immediates

* Check for op_count before checking for mem op at -1 index.

* Update memory operand flags.

* Pass imm/reg memory ops in set_imm/reg to set_mem.

* Add missing set_sme_operand call and fix assert.

* Remove CS_OP_MEM flag before entering switch.

* Preidcates are registers.

* Add shift info always to the previous operand

* Check for generic system regs

* Handle NumLanes = 0 LaneKind = q case

* Replace printImm call with normal print logic. Otherwise ops get added twice to detail.

* Handle FP operands in printOperand.

* Add access information to float operands.

* Rewrite SME matrix handling.

* Set correct SME layouts and allow for immediate range sme offsets.

* Handle cases of unknown system alias by setting their raw values

* Update cstool and header file with new SME offset handling

* Handle SME Tile lists.

* Fix build error in cstest

* Update MC tests for AArch64

* Handle TLBI operands and fix printing bug.

* Fix: Print signed value as signed.

* Add more system alias to detail.

* Remove duplicate hex prefix

* Set correct values for the register info

* Replace tabs with white spaces

* Move string append logic to own function.

* Set DecodeComplete = true before decoding (as originally in the LLVM code).

* Change type of feature argument, since only LLVM features are passed, not CS groups.

* Imitate lower_bound for the index table binary search.

* Remove trailing comments from test files.

* Print shift amount in decimal

* Save detail of shift alias instructions.

* Add extension details fot ext instruction alias

* Print LSB and width in decimal

* Fix LLVM bug. The feature check for V8_2a doesn't check if all features are enabled.

* Fix lower_bounds check.
For m == 0 we wrap around 0 of cause.

* Fix feature check. Add check for FeatureAll since it includes XS

* Operate on temporary MCInst when trying decoding.

* Add lower_bound behavior to IndexTypeStr binsearch.

* Fix MC tests which were incorrect because of missing FeatureAll check

* Add Alias handling for AArch64

* Update system operands with SYSIMM types and add additional sysop category.

* Add macros for meta programming (ARM64 <-> AArch64 selection).

* Fix union/struct confusion and add raw_value member to uninions.

* Allow to set Syntax and mode options for AArch64

* Fix build warning by using correct type

* Print shift value in decimal

* Add missing call to add_cs_detail.

* Update name map files with normalized names.

* Remove unused function

* Add check if detail should be filled.

* Fill detail for real instructions if only real detail is requested.

* Add always the extension.

* Make dir creation log message debug level

* Implement ADR immediate operand printer.

See: capstone-engine/llvm-capstone@c3484b1

* Check for flag registers beeing written and update flag.

* Move multiple CondCode helpers to aarch64.h because they are so freaking useful.

+ Print CC if it is EQ

* Fix incorrectly initialized CC and VectorLayout.

* Add LSL shift type for extensions.

* Fix case when shift amount is 0

* Fix post-index memory instructions.

* Pass raw immediate through getShiftValue to extract actual shift amount

* Setup AArch64 detail ops.

* Add flag for operands part of a list.

* Set vector indices for all relevant registers.

* Add missing call to add_cs_detail for postIncOperands

* Add ugly yet reliable way to determine post-index addressing mode

* Add support for old Capstone register alias.

* Remove leading space before some alias mnemonics.

* add AARCH64 to `cmake.sh`

* add HAS_AARCH64 to `cs.c`

* should probably just reference `cs_operand.h` in `aarch64.h`

* hint compiler at `AArch64_SYSREG` enum type for casting purposes

* update `Makefile` for AARCH64

leaves `CAPSTONE_HAS_ARM64` supported

* `testFeatureBits` platform function check

`testFeatureBits` should check if the platform function is visible first

* update tests to use AARCH64 convention

* hack: avoid enum casts for `MCInst` Values

Apple compiler really hates typecasting a enum, even if bounded from a unsigned. Lets set the raw_value directly

is a hack and needs proper review

* Check for present detail before accessing it.

* Add CS only groups

* Use general map ins_op type

* Fix build warning about str size computation.

* Disable warning about unitialized value for GCC 11.

Imm is initialized and the warning does not appear
in later versions.

* Use correct include guard for PPC

* Add missing requirements

* Update SystemOperand enums.

* Fix overlapping comparison warning

* Fix reachable assert where OpNum is not of type IMM

* Handle 0.0 operand for fcmp

* Fix incorrect variable passed.

* Fix for MacOS which doesn't know the warning and throws another one.

* Make getExtendEncoding static to fix build warning on MSVC.

* Fix build error: 'missing binary operator before token' by checking __GNUC__

* Add string search to add vector layout info.

* Add missing mem disponents of several ldr and str instructions.

* Add 0 immediates to several instructions.

* Rename v regs to q and d variant.

The cs_regname API can not pass the variant name of the register requested.
So we simply emit the default variant name.

* Fix incorrect enum value.

* Fix tests for system operands.

* Fix syntax issues in tests.

* Rename Arm64 -> AArch64 Python bindings.

* Fix Python bindings C structs.

* Fix generation of constants (ARMCC skipped because it starts with ARM)

* Update const files

* Remove -Wmaybe-uninitialized warning since it fails fuzz build

* Add missing comma

* Fix case

* Fix AArch64 Python bindings:

- Do not generate constants automatically (dscript is way too buggy).
- Update printing of details.

* Rename ARM64 -> AArch64 in test_corpus.py

* Rename test_arm64 -> test_aarch64

* Rename ARM-64 -> AArch64

* Fix diff CI test by disassembling AArch64 at former ARM64 place

* Fix several wrong types and remove unnecessary memebers from Python binding

* Fix: Same printing format of detail for cstool, test_ and test_*.py

* Fix: pass correct op index for mov alias with op[1] == reg wzr.

* Set prfm op manuall in case of unnown sysop. set_imm would add it to an memory operand wihtout base.

* Fix: If barrier ops are not set an assert is reached.

We fix it here by simply getting the immediate as the printing code does.

---------

Co-authored-by: Peace-Maker <[email protected]>
Co-authored-by: Dayton <[email protected]>

.gitignore

@@ -37,7 +37,7 @@ bindings/ocaml/*.cmxa
 bindings/ocaml/*.mli
 bindings/ocaml/test
 bindings/ocaml/test_arm
-bindings/ocaml/test_arm64
+bindings/ocaml/test_aarch64
 bindings/ocaml/test_basic
 bindings/ocaml/test_mips
 bindings/ocaml/test_x86
@@ -54,7 +54,7 @@ tests/test_basic
 tests/test_detail
 tests/test_iter
 tests/test_arm
-tests/test_arm64
+tests/test_aarch64
 tests/test_mips
 tests/test_x86
 tests/test_ppc

CMakeLists.txt

@@ -45,8 +45,8 @@ option(CAPSTONE_ARCHITECTURE_DEFAULT "Whether architectures are enabled by defau
 option(CAPSTONE_DEBUG "Whether to enable extra debug assertions" OFF)
 option(CAPSTONE_INSTALL "Generate install target" ${PROJECT_IS_TOP_LEVEL})
 
-set(SUPPORTED_ARCHITECTURES ARM ARM64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE)
-set(SUPPORTED_ARCHITECTURE_LABELS ARM ARM64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore)
+set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE)
+set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore)
 
 list(LENGTH SUPPORTED_ARCHITECTURES count)
 math(EXPR count "${count}-1")
@@ -123,7 +123,7 @@ set(HEADERS_ENGINE
 )
 
 set(HEADERS_COMMON
-    include/capstone/arm64.h
+    include/capstone/aarch64.h
     include/capstone/arm.h
     include/capstone/capstone.h
     include/capstone/cs_operand.h
@@ -181,35 +181,35 @@ if(CAPSTONE_ARM_SUPPORT)
     set(TEST_SOURCES ${TEST_SOURCES} test_arm.c)
 endif()
 
-if(CAPSTONE_ARM64_SUPPORT)
-    add_definitions(-DCAPSTONE_HAS_ARM64)
-    set(SOURCES_ARM64
+if(CAPSTONE_AARCH64_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_AARCH64)
+    set(SOURCES_AARCH64
         arch/AArch64/AArch64BaseInfo.c
         arch/AArch64/AArch64Disassembler.c
+        arch/AArch64/AArch64DisassemblerExtension.c
         arch/AArch64/AArch64InstPrinter.c
         arch/AArch64/AArch64Mapping.c
         arch/AArch64/AArch64Module.c
     )
-    set(HEADERS_ARM64
+    set(HEADERS_AARCH64
         arch/AArch64/AArch64AddressingModes.h
         arch/AArch64/AArch64BaseInfo.h
-        arch/AArch64/AArch64Disassembler.h
+        arch/AArch64/AArch64DisassemblerExtension.h
         arch/AArch64/AArch64InstPrinter.h
+        arch/AArch64/AArch64Linkage.h
         arch/AArch64/AArch64Mapping.h
         arch/AArch64/AArch64GenAsmWriter.inc
         arch/AArch64/AArch64GenDisassemblerTables.inc
         arch/AArch64/AArch64GenInstrInfo.inc
         arch/AArch64/AArch64GenRegisterInfo.inc
         arch/AArch64/AArch64GenRegisterName.inc
-        arch/AArch64/AArch64GenRegisterV.inc
         arch/AArch64/AArch64GenSubtargetInfo.inc
         arch/AArch64/AArch64GenSystemOperands.inc
-        arch/AArch64/AArch64GenSystemOperands_enum.inc
-        arch/AArch64/AArch64MappingInsn.inc
-        arch/AArch64/AArch64MappingInsnName.inc
-        arch/AArch64/AArch64MappingInsnOp.inc
+        arch/AArch64/AArch64GenCSMappingInsn.inc
+        arch/AArch64/AArch64GenCSMappingInsnName.inc
+        arch/AArch64/AArch64GenCSMappingInsnOp.inc
     )
-    set(TEST_SOURCES ${TEST_SOURCES} test_arm64.c)
+    set(TEST_SOURCES ${TEST_SOURCES} test_aarch64.c)
 endif()
 
 if(CAPSTONE_MIPS_SUPPORT)
@@ -576,7 +576,7 @@ endif()
 set(ALL_SOURCES
     ${SOURCES_ENGINE}
     ${SOURCES_ARM}
-    ${SOURCES_ARM64}
+    ${SOURCES_AARCH64}
     ${SOURCES_MIPS}
     ${SOURCES_PPC}
     ${SOURCES_X86}
@@ -599,7 +599,7 @@ set(ALL_HEADERS
     ${HEADERS_COMMON}
     ${HEADERS_ENGINE}
     ${HEADERS_ARM}
-    ${HEADERS_ARM64}
+    ${HEADERS_AARCH64}
     ${HEADERS_MIPS}
     ${HEADERS_PPC}
     ${HEADERS_X86}
@@ -662,7 +662,7 @@ endif()
 
 source_group("Source\\Engine" FILES ${SOURCES_ENGINE})
 source_group("Source\\ARM" FILES ${SOURCES_ARM})
-source_group("Source\\ARM64" FILES ${SOURCES_ARM64})
+source_group("Source\\AARCH64" FILES ${SOURCES_AARCH64})
 source_group("Source\\Mips" FILES ${SOURCES_MIPS})
 source_group("Source\\PowerPC" FILES ${SOURCES_PPC})
 source_group("Source\\Sparc" FILES ${SOURCES_SPARC})
@@ -683,7 +683,7 @@ source_group("Source\\TriCore" FILES ${SOURCES_TRICORE})
 source_group("Include\\Common" FILES ${HEADERS_COMMON})
 source_group("Include\\Engine" FILES ${HEADERS_ENGINE})
 source_group("Include\\ARM" FILES ${HEADERS_ARM})
-source_group("Include\\ARM64" FILES ${HEADERS_ARM64})
+source_group("Include\\AARCH64" FILES ${HEADERS_AARCH64})
 source_group("Include\\Mips" FILES ${HEADERS_MIPS})
 source_group("Include\\PowerPC" FILES ${HEADERS_PPC})
 source_group("Include\\Sparc" FILES ${HEADERS_SPARC})

COMPILE.TXT

@@ -148,7 +148,7 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
 (5) Cross-compile for Android
 
   To cross-compile for Android (smartphone/tablet), Android NDK is required.
-  NOTE: Only ARM and ARM64 are currently supported.
+  NOTE: Only ARM and AARCH64 are currently supported.
 
 	$ NDK=/android/android-ndk-r10e ./make.sh cross-android arm
   or

COMPILE_CMAKE.TXT

@@ -20,7 +20,7 @@ Get CMake for free from http://www.cmake.org.
   run "cmake" with the unwanted archs disabled (set to 0) as followings.
 
   - CAPSTONE_ARM_SUPPORT: support ARM. Run cmake with -DCAPSTONE_ARM_SUPPORT=0 to remove ARM.
-  - CAPSTONE_ARM64_SUPPORT: support ARM64. Run cmake with -DCAPSTONE_ARM64_SUPPORT=0 to remove ARM64.
+  - CAPSTONE_AARCH64_SUPPORT: support AARCH64. Run cmake with -DCAPSTONE_AARCH64_SUPPORT=0 to remove AARCH64.
   - CAPSTONE_M680X_SUPPORT: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X.
   - CAPSTONE_M68K_SUPPORT: support M68K. Run cmake with -DCAPSTONE_M68K_SUPPORT=0 to remove M68K.
   - CAPSTONE_MIPS_SUPPORT: support Mips. Run cmake with -DCAPSTONE_MIPS_SUPPORT=0 to remove Mips.
@@ -112,7 +112,7 @@ Get CMake for free from http://www.cmake.org.
     ../cmake.sh x86
 
   Will just target the x86 architecture. The list of available architectures is: ARM,
-  ARM64, M68K, MIPS, PowerPC, Sparc, SystemZ, XCore, x86, TMS320C64x, M680x, EVM, MOS65XX,
+  AARCH64, M68K, MIPS, PowerPC, Sparc, SystemZ, XCore, x86, TMS320C64x, M680x, EVM, MOS65XX,
   WASM, BPF, RISCV.
 
 (4) You can also create an installation image with cmake, by using the 'install' target.

COMPILE_MSVC.TXT

@@ -31,7 +31,7 @@ versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required.
   to customize Capstone library, as followings.
 
   - CAPSTONE_HAS_ARM: support ARM. Delete this to remove ARM support.
-  - CAPSTONE_HAS_ARM64: support ARM64. Delete this to remove ARM64 support.
+  - CAPSTONE_HAS_AARCH64: support AARCH64. Delete this to remove AARCH64 support.
   - CAPSTONE_HAS_M68K: support M68K. Delete this to remove M68K support.
   - CAPSTONE_HAS_MIPS: support Mips. Delete this to remove Mips support.
   - CAPSTONE_HAS_POWERPC: support PPC. Delete this to remove PPC support.

HACK.TXT

@@ -5,7 +5,7 @@ Capstone source is organized as followings.
 
 .                   <- core engine + README + COMPILE.TXT etc
 ├── arch            <- code handling disasm engine for each arch
-│   ├── AArch64     <- ARM64 (aka ARMv8) engine
+│   ├── AArch64     <- AArch64 engine
 │   ├── ARM         <- ARM engine
 │   ├── BPF         <- Berkeley Packet Filter engine
 │   ├── EVM         <- Ethereum engine

MCInst.c

@@ -144,7 +144,7 @@ void MCOperand_setReg(MCOperand *op, unsigned Reg)
 	op->RegVal = Reg;
 }
 
-int64_t MCOperand_getImm(MCOperand *op)
+int64_t MCOperand_getImm(const MCOperand *op)
 {
 	return op->ImmVal;
 }
@@ -281,11 +281,22 @@ uint64_t MCInst_getOpVal(MCInst *MI, unsigned OpNum)
 		return MCOperand_getImm(op);
 	else
 		assert(0 && "Operand type not handled in this getter.");
-	return false;
+	return MCOperand_getImm(op);
 }
 
 void MCInst_setIsAlias(MCInst *MI, bool Flag) {
 	assert(MI);
 	MI->isAliasInstr = Flag;
 	MI->flat_insn->is_alias = Flag;
 }
+
+/// @brief Copies the relevant members of a temporary MCInst to
+/// the main MCInst. This is used if TryDecode was run on a temporary MCInst.
+/// @param MI The main MCInst
+/// @param TmpMI The temporary MCInst.
+void MCInst_updateWithTmpMI(MCInst *MI, MCInst *TmpMI) {
+	MI->size = TmpMI->size;
+	MI->Opcode = TmpMI->Opcode;
+	assert(MI->size < MAX_MC_OPS);
+	memcpy(MI->Operands, TmpMI->Operands, sizeof(MI->Operands[0]) * MI->size);
+}

MCInst.h

@@ -68,7 +68,7 @@ unsigned MCOperand_getReg(const MCOperand *op);
 /// setReg - Set the register number.
 void MCOperand_setReg(MCOperand *op, unsigned Reg);
 
-int64_t MCOperand_getImm(MCOperand *op);
+int64_t MCOperand_getImm(const MCOperand *op);
 
 void MCOperand_setImm(MCOperand *op, int64_t Val);
 
@@ -171,4 +171,6 @@ static inline bool MCInst_isAlias(const MCInst *MI) {
 	return MI->isAliasInstr;
 }
 
+void MCInst_updateWithTmpMI(MCInst *MI, MCInst *TmpMI);
+
 #endif

MCInstPrinter.c

@@ -7,17 +7,27 @@
 
 extern bool ARM_getFeatureBits(unsigned int mode, unsigned int feature);
 extern bool PPC_getFeatureBits(unsigned int mode, unsigned int feature);
+extern bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature);
 
 static bool testFeatureBits(const MCInst *MI, uint32_t Value)
 {
 	assert(MI && MI->csh);
 	switch (MI->csh->arch) {
 	default:
 		assert(0 && "Not implemented for current arch.");
+		return false;
+#ifdef CAPSTONE_HAS_ARM
 	case CS_ARCH_ARM:
 		return ARM_getFeatureBits(MI->csh->mode, Value);
+#endif
+#ifdef CAPSTONE_HAS_POWERPC
 	case CS_ARCH_PPC:
 		return PPC_getFeatureBits(MI->csh->mode, Value);
+#endif
+#ifdef CAPSTONE_HAS_AARCH64
+	case CS_ARCH_AARCH64:
+		return AArch64_getFeatureBits(MI->csh->mode, Value);
+#endif
 	}
 }
 
@@ -185,6 +195,11 @@ unsigned int binsearch_IndexTypeEncoding(const struct IndexType *index, size_t s
 	while(left <= right) {
 		m = (left + right) / 2;
 		if (encoding == index[m].encoding) {
+			// LLVM actually uses lower_bound for the index table search
+			// Here we need to check if a previous entry is of the same encoding
+			// and return the first one.
+			while (m > 0 && encoding == index[m - 1].encoding)
+				--m;
 			return m;
 		}
 
@@ -218,6 +233,11 @@ unsigned int binsearch_IndexTypeStrEncoding(const struct IndexTypeStr *index, si
 	while(left <= right) {
 		m = (left + right) / 2;
 		if (strcmp(name, index[m].name) == 0) {
+			// LLVM actually uses lower_bound for the index table search
+			// Here we need to check if a previous entry is of the same encoding
+			// and return the first one.
+			while (m > 0 && (strcmp(name, index[m - 1].name) == 0))
+				--m;
 			return m;
 		}
 

Makefile

@@ -126,14 +126,15 @@ ifneq (,$(findstring arm,$(CAPSTONE_ARCHS)))
 	LIBOBJ_ARM += $(LIBSRC_ARM:%.c=$(OBJDIR)/%.o)
 endif
 
-DEP_ARM64 =
-DEP_ARM64 += $(wildcard arch/AArch64/AArch64*.inc)
+DEP_AARCH64 =
+DEP_AARCH64 += $(wildcard arch/AArch64/AArch64*.inc)
 
-LIBOBJ_ARM64 =
+LIBOBJ_AARCH64 =
 ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS)))
 	CFLAGS += -DCAPSTONE_HAS_ARM64
-	LIBSRC_ARM64 += $(wildcard arch/AArch64/AArch64*.c)
-	LIBOBJ_ARM64 += $(LIBSRC_ARM64:%.c=$(OBJDIR)/%.o)
+	CFLAGS += -DCAPSTONE_HAS_AARCH64
+	LIBSRC_AARCH64 += $(wildcard arch/AArch64/AArch64*.c)
+	LIBOBJ_AARCH64 += $(LIBSRC_AARCH64:%.c=$(OBJDIR)/%.o)
 endif
 
 
@@ -327,7 +328,7 @@ endif
 
 LIBOBJ =
 LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o $(OBJDIR)/MCInst.o $(OBJDIR)/MCInstPrinter.o $(OBJDIR)/Mapping.o
-LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_SH)
+LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_AARCH64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_SH)
 LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF)
 LIBOBJ += $(LIBOBJ_TRICORE)
 
@@ -448,7 +449,7 @@ endif
 $(LIBOBJ): config.mk
 
 $(LIBOBJ_ARM): $(DEP_ARM)
-$(LIBOBJ_ARM64): $(DEP_ARM64)
+$(LIBOBJ_AARCH64): $(DEP_AARCH64)
 $(LIBOBJ_M68K): $(DEP_M68K)
 $(LIBOBJ_MIPS): $(DEP_MIPS)
 $(LIBOBJ_PPC): $(DEP_PPC)
@@ -550,9 +551,9 @@ dist:
 	git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz
 	git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip
 
-TESTS  = test_basic test_detail test_arm test_arm64 test_m68k test_mips test_ppc test_sparc test_tricore
+TESTS  = test_basic test_detail test_arm test_aarch64 test_m68k test_mips test_ppc test_sparc test_tricore
 TESTS += test_systemz test_x86 test_xcore test_iter test_evm test_riscv test_mos65xx test_wasm test_bpf
-TESTS += test_basic.static test_detail.static test_arm.static test_arm64.static
+TESTS += test_basic.static test_detail.static test_arm.static test_aarch64.static
 TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static
 TESTS += test_systemz.static test_x86.static test_xcore.static test_m680x.static
 TESTS += test_skipdata test_skipdata.static test_iter.static test_evm.static test_riscv.static

Mapping.c

@@ -312,6 +312,7 @@ const cs_ac_type mapping_get_op_access(MCInst *MI, unsigned OpNum,
 DEFINE_get_detail_op(arm, ARM);
 DEFINE_get_detail_op(ppc, PPC);
 DEFINE_get_detail_op(tricore, TriCore);
+DEFINE_get_detail_op(aarch64, AArch64);
 
 /// Returns true if for this architecture the
 /// alias operands should be filled.
@@ -363,7 +364,7 @@ void map_set_alias_id(MCInst *MI, const SStream *O, const name_map *alias_mnem_i
 	for (; j < sizeof(alias_mnem) - 1; ++j, ++i) {
 		if (!asm_str_buf[i] || asm_str_buf[i] == ' ' || asm_str_buf[i] == '\t')
 			break;
-		alias_mnem[j] = O->buffer[i];
+		alias_mnem[j] = asm_str_buf[i];
 	}
 
 	MI->flat_insn->alias_id = name2id(alias_mnem_id_map, map_size, alias_mnem);

Mapping.h

@@ -42,7 +42,7 @@ unsigned short insn_find(const insn_map *m, unsigned int max, unsigned int id,
 unsigned int find_cs_id(unsigned MC_Opcode, const insn_map *imap,
 			unsigned imap_size);
 
-#define MAX_NO_DATA_TYPES 10
+#define MAX_NO_DATA_TYPES 16
 
 ///< A LLVM<->CS Mapping entry of an MCOperand.
 typedef struct {
@@ -120,6 +120,7 @@ void map_cs_id(MCInst *MI, const insn_map *imap, unsigned int imap_size);
 DECL_get_detail_op(arm, ARM);
 DECL_get_detail_op(ppc, PPC);
 DECL_get_detail_op(tricore, TriCore);
+DECL_get_detail_op(aarch64, AArch64);
 
 /// Increments the detail->arch.op_count by one.
 #define DEFINE_inc_detail_op_count(arch, ARCH) \
@@ -141,6 +142,8 @@ DEFINE_inc_detail_op_count(ppc, PPC);
 DEFINE_dec_detail_op_count(ppc, PPC);
 DEFINE_inc_detail_op_count(tricore, TriCore);
 DEFINE_dec_detail_op_count(tricore, TriCore);
+DEFINE_inc_detail_op_count(aarch64, AArch64);
+DEFINE_dec_detail_op_count(aarch64, AArch64);
 
 /// Returns true if a memory operand is currently edited.
 static inline bool doing_mem(const MCInst *MI)
@@ -165,6 +168,7 @@ static inline void set_doing_mem(const MCInst *MI, bool status)
 DEFINE_get_arch_detail(arm, ARM);
 DEFINE_get_arch_detail(ppc, PPC);
 DEFINE_get_arch_detail(tricore, TriCore);
+DEFINE_get_arch_detail(aarch64, AArch64);
 
 static inline bool detail_is_set(const MCInst *MI)
 {
@@ -178,12 +182,6 @@ static inline cs_detail *get_detail(const MCInst *MI)
 	return MI->flat_insn->detail;
 }
 
-static inline bool set_detail_ops(const MCInst *MI)
-{
-	assert(MI && MI->flat_insn);
-	return MI->fillDetailOps;
-}
-
 /// Returns if the given instruction is an alias instruction.
 #define RETURN_IF_INSN_IS_ALIAS(MI) \
 do { \

README.md

@@ -12,7 +12,7 @@ disasm engine for binary analysis and reversing in the security community.
 Created by Nguyen Anh Quynh, then developed and maintained by a small community,
 Capstone offers some unparalleled features:
 
-- Support multiple hardware architectures: ARM, ARM64 (ARMv8), BPF, Ethereum VM,
+- Support multiple hardware architectures: ARM, AArch64, BPF, Ethereum VM,
   M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ,
   TMS320C64X, TriCore, Webassembly, XCore and X86 (16, 32, 64).