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xtensa: fix all
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@imbillow
imbillow committed Nov 3, 2024
1 parent 493cdf4 commit c143bc1
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Showing 6 changed files with 102 additions and 66 deletions.
61 changes: 29 additions & 32 deletions arch/Xtensa/XtensaDisassembler.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -913,12 +913,8 @@ static DecodeStatus readInstruction16(MCInst *MI, const uint8_t *Bytes,
return MCDisassembler_Fail;
}

if (!IsLittleEndian) {
CS_ASSERT(0 && "Big-endian mode currently is not supported!");
} else {
*Insn = readBytes16(MI, Bytes);
*Size = 2;
}
*Insn = readBytes16(MI, Bytes);
*Size = 2;

return MCDisassembler_Success;
}
Expand All @@ -935,14 +931,10 @@ static DecodeStatus readInstruction24(MCInst *MI, const uint8_t *Bytes,
return MCDisassembler_Fail;
}

if (!IsLittleEndian) {
CS_ASSERT("Big-endian mode currently is not supported!");
} else {
if (CheckTIE && (Bytes[0] & 0x8) != 0)
return MCDisassembler_Fail;
*Insn = readBytes24(MI, Bytes);
*Size = 3;
}
if (CheckTIE && (Bytes[0] & 0x8) != 0)
return MCDisassembler_Fail;
*Insn = readBytes24(MI, Bytes);
*Size = 3;

return MCDisassembler_Success;
}
Expand All @@ -959,14 +951,10 @@ static DecodeStatus readInstruction32(MCInst *MI, const uint8_t *Bytes,
return MCDisassembler_Fail;
}

if (!IsLittleEndian) {
CS_ASSERT("Big-endian mode currently is not supported!");
} else {
if ((Bytes[0] & 0x8) == 0)
return MCDisassembler_Fail;
*Insn = readBytes32(MI, Bytes);
*Size = 4;
}
if ((Bytes[0] & 0x8) == 0)
return MCDisassembler_Fail;
*Insn = readBytes32(MI, Bytes);
*Size = 4;

return MCDisassembler_Success;
}
Expand All @@ -983,13 +971,9 @@ static DecodeStatus readInstructionN(const uint8_t *Bytes, size_t BytesLen,
return MCDisassembler_Fail;
}

if (!IsLittleEndian) {
CS_ASSERT("Big-endian mode currently is not supported!");
} else {
*Insn = 0;
for (unsigned i = 0; i < InstSize; i++)
*Insn |= (Bytes[i] << 8 * i);
}
*Insn = 0;
for (unsigned i = 0; i < InstSize; i++)
*Insn |= (Bytes[i] << 8 * i);

*Size = InstSize;
return MCDisassembler_Success;
Expand Down Expand Up @@ -1020,13 +1004,14 @@ static bool hasESP32S3Ops()
{
return true;
}

static bool hasHIFI3()
{
return true;
}
DecodeStatus getInstruction(MCInst *MI, uint64_t *Size, const uint8_t *Bytes,
size_t BytesLen, uint64_t Address, SStream *CS)

static DecodeStatus getInstruction(MCInst *MI, uint64_t *Size,
const uint8_t *Bytes, size_t BytesLen,
uint64_t Address)
{
uint64_t Insn;
DecodeStatus Result;
Expand Down Expand Up @@ -1104,3 +1089,15 @@ DecodeStatus getInstruction(MCInst *MI, uint64_t *Size, const uint8_t *Bytes,
}
return Result;
}

DecodeStatus Xtensa_LLVM_getInstruction(MCInst *MI, uint16_t *size16,
const uint8_t *Bytes,
unsigned BytesSize, uint64_t Address)
{
uint64_t size64;
DecodeStatus status =
getInstruction(MI, &size64, Bytes, BytesSize, Address);
CS_ASSERT_RET_VAL(size64 < 0xffff, MCDisassembler_Fail);
*size16 = size64;
return status;
}
28 changes: 14 additions & 14 deletions arch/Xtensa/XtensaGenAsmWriter.inc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7901,8 +7901,8 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
break;
case 11:
// AE_MOVI
printImmOperand_-16_47_1(MI, 1, O);
return;
printImmOperand_minus16_47_1(MI, 1, O);
return;
break;
case 12:
// AE_MULA16X4, AE_MULAF16X4SS, AE_MULAFD24X2_FIR_H, AE_MULAFD24X2_FIR_L,...
Expand Down Expand Up @@ -8119,32 +8119,32 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
break;
case 14:
// AE_L16M_I, AE_L16_I, AE_S16M_L_I, AE_S16_0_I
printImmOperand_-16_14_2(MI, 2, O);
return;
printImmOperand_minus16_14_2(MI, 2, O);
return;
break;
case 15:
// AE_L16M_IU, AE_L16_IP, AE_S16M_L_IU, AE_S16_0_IP
printImmOperand_-16_14_2(MI, 3, O);
return;
printImmOperand_minus16_14_2(MI, 3, O);
return;
break;
case 16:
// AE_L16M_XC, AE_L16M_XU, AE_L16X2M_XC, AE_L16X2M_XU, AE_L16X4_XC, AE_L1...
printOperand(MI, 3, O);
break;
case 17:
// AE_L16X2M_I, AE_L32F24_I, AE_L32M_I, AE_L32_I, AE_S16X2M_I, AE_S24RA64...
printImmOperand_-32_28_4(MI, 2, O);
return;
printImmOperand_minus32_28_4(MI, 2, O);
return;
break;
case 18:
// AE_L16X2M_IU, AE_L32F24_IP, AE_L32M_IU, AE_L32_IP, AE_S16X2M_IU, AE_S2...
printImmOperand_-32_28_4(MI, 3, O);
return;
printImmOperand_minus32_28_4(MI, 3, O);
return;
break;
case 19:
// AE_L16X4_I, AE_L32X2F24_I, AE_L32X2_I, AE_L64_I, AE_LALIGN64_I, AE_S16...
printImmOperand_-64_56_8(MI, 2, O);
return;
printImmOperand_minus64_56_8(MI, 2, O);
return;
break;
case 20:
// AE_L16X4_IP, AE_L32X2F24_IP, AE_L32X2_IP, AE_S16X4_IP, AE_S32X2F24_IP,...
Expand All @@ -8153,8 +8153,8 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
break;
case 21:
// AE_L64_IP, AE_S64_IP
printImmOperand_-64_56_8(MI, 3, O);
return;
printImmOperand_minus64_56_8(MI, 3, O);
return;
break;
case 22:
// AE_LA16X4_IC, AE_LA16X4_IP, AE_LA16X4_RIC, AE_LA16X4_RIP, AE_LA24X2_IC...
Expand Down
8 changes: 4 additions & 4 deletions arch/Xtensa/XtensaGenCSOpGroup.inc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -29,11 +29,11 @@
Xtensa_OP_GROUP_Imm1n_15_AsmOperand = 15,
Xtensa_OP_GROUP_Imm8_sh8_AsmOperand = 16,
Xtensa_OP_GROUP_Imm1_16_AsmOperand = 17,
Xtensa_OP_GROUP_ImmOperand_-16_14_2 = 18,
Xtensa_OP_GROUP_ImmOperand_-32_28_4 = 19,
Xtensa_OP_GROUP_ImmOperand_-64_56_8 = 20,
Xtensa_OP_GROUP_ImmOperand_minus16_14_2 = 18,
Xtensa_OP_GROUP_ImmOperand_minus32_28_4 = 19,
Xtensa_OP_GROUP_ImmOperand_minus64_56_8 = 20,
Xtensa_OP_GROUP_ImmOperand_0_56_8 = 21,
Xtensa_OP_GROUP_ImmOperand_-16_47_1 = 22,
Xtensa_OP_GROUP_ImmOperand_minus16_47_1 = 22,
Xtensa_OP_GROUP_ImmOperand_0_3_1 = 23,
Xtensa_OP_GROUP_Uimm4_AsmOperand = 24,
Xtensa_OP_GROUP_Imm7_22_AsmOperand = 25,
Expand Down
31 changes: 30 additions & 1 deletion arch/Xtensa/XtensaInstPrinter.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,6 @@ static void printOperand(MCInst *MI, const int op_num, SStream *O)
else
CS_ASSERT("Invalid operand");
}

static inline void printMemOperand(MCInst *MI, int OpNum, SStream *OS)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_MemOperand, OpNum);
Expand Down Expand Up @@ -681,6 +680,31 @@ static inline void printOffset_64_16_AsmOperand(MCInst *MI, int OpNum,
printOperand(MI, OpNum, O);
}

#define IMPL_printImmOperand(N, L, H, S) \
static void printImmOperand_##N(MCInst *MI, int OpNum, SStream *O) \
{ \
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_ImmOperand_##N, \
OpNum); \
MCOperand *MC = MCInst_getOperand(MI, (OpNum)); \
if (MCOperand_isImm(MC)) { \
int64_t Value = MCOperand_getImm(MC); \
CS_ASSERT((Value >= L && Value <= H && \
((Value % S) == 0)) && \
"Invalid argument"); \
printInt64(O, Value); \
} else { \
printOperand(MI, OpNum, O); \
} \
}

IMPL_printImmOperand(minus64_56_8, -64, 56, 8);
IMPL_printImmOperand(minus32_28_4, -32, 28, 4);
IMPL_printImmOperand(minus16_47_1, -16, 47, 1);
IMPL_printImmOperand(minus16_14_2, -16, 14, 2);
IMPL_printImmOperand(0_56_8, 0, 56, 8);
IMPL_printImmOperand(0_3_1, 0, 3, 1);
IMPL_printImmOperand(0_63_1, 0, 63, 1);

#include "XtensaGenAsmWriter.inc"

static void printInst(MCInst *MI, uint64_t Address, const char *Annot,
Expand Down Expand Up @@ -714,3 +738,8 @@ void Xtensa_LLVM_printInstruction(MCInst *MI, uint64_t Address, SStream *O)
{
printInst(MI, Address, NULL, O);
}

const char *Xtensa_LLVM_getRegisterName(unsigned RegNo)
{
return getRegisterName(RegNo);
}
4 changes: 4 additions & 0 deletions arch/Xtensa/XtensaMapping.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -164,6 +164,10 @@ void Xtensa_reg_access(const cs_insn *insn, cs_regs regs_read,

void Xtensa_add_cs_detail_0(MCInst *MI, xtensa_op_group op_group, int op_num)
{
if (!detail_is_set(MI)) {
return;
}

cs_xtensa_op *xop = Xtensa_get_detail_op(MI, 0);
switch (op_group) {
case Xtensa_OP_GROUP_Operand: {
Expand Down
36 changes: 21 additions & 15 deletions suite/auto-sync/src/autosync/cpptranslator/saved_patches.json
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3433,14 +3433,14 @@
"edit": ""
},
"printBranchTarget": {
"apply_type": "NEW",
"old_hash": "e632d7f4e5e1ab69af65ca0254bb924564ef5a01c2356ad92404fd7c4c3b7590",
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"edit": ""
},
Expand Down Expand Up @@ -3518,25 +3518,25 @@
},
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"apply_type": "OLD",
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"printL32RTarget": {
"apply_type": "NEW",
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"printLoopTarget": {
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"edit": ""
},
Expand All @@ -3548,13 +3548,13 @@
},
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"edit": ""
},
Expand All @@ -3566,7 +3566,7 @@
},
"printOffset8m8_AsmOperand": {
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Expand Down Expand Up @@ -3614,7 +3614,7 @@
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Expand Down Expand Up @@ -3677,6 +3677,12 @@
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}

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