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Xtensa: fix
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@imbillow
imbillow committed Jun 6, 2024
1 parent d2d3a05 commit 45cfa7b
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Showing 14 changed files with 236 additions and 155 deletions.
2 changes: 2 additions & 0 deletions CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,8 @@ if(CMAKE_SOURCE_DIR STREQUAL CMAKE_BINARY_DIR)
message(FATAL_ERROR "In-tree builds are not supported. Run CMake from a separate directory: cmake -B build")
endif()

set(BUILD_RPATH_USE_ORIGIN true)

# Detect whether capstone is compiled as top-level or a subdirectory
set(PROJECT_IS_TOP_LEVEL OFF)
if(CMAKE_CURRENT_SOURCE_DIR STREQUAL CMAKE_SOURCE_DIR)
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2 changes: 2 additions & 0 deletions Mapping.h
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Original file line number Diff line number Diff line change
Expand Up @@ -152,6 +152,8 @@ DEFINE_inc_detail_op_count(alpha, Alpha);
DEFINE_dec_detail_op_count(alpha, Alpha);
DEFINE_inc_detail_op_count(hppa, HPPA);
DEFINE_dec_detail_op_count(hppa, HPPA);
DEFINE_inc_detail_op_count(xtensa, Xtensa);
DEFINE_dec_detail_op_count(xtensa, Xtensa);

/// Returns true if a memory operand is currently edited.
static inline bool doing_mem(const MCInst *MI)
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32 changes: 18 additions & 14 deletions arch/Xtensa/XtensaDisassembler.c
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Original file line number Diff line number Diff line change
Expand Up @@ -235,22 +235,15 @@ static DecodeStatus decodeMem32Operand(MCInst *Inst, uint64_t Imm,
/// Read three bytes from the ArrayRef and return 24 bit data
static DecodeStatus readInstruction24(const uint8_t *Bytes,
const unsigned BytesSize, uint64_t *Size,
uint32_t *Insn, bool IsLittleEndian)
uint32_t *Insn)
{
// We want to read exactly 3 Bytes of data.
if (BytesSize < 3) {
*Size = 0;
return MCDisassembler_Fail;
}

if (!IsLittleEndian) {
report_fatal_error(
"Big-endian mode currently is not supported!");
return MCDisassembler_Fail;
} else {
*Insn = (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
}

*Insn = (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
*Size = 3;
return MCDisassembler_Success;
}
Expand All @@ -262,18 +255,29 @@ DecodeToMCInst(decode_to_MCInst, field_from_inst, uint32_t);
DecodeInstruction(decodeInstruction, field_from_inst, decode_to_MCInst,
uint32_t);

DecodeStatus getInstruction(MCInst *MI, uint64_t *Size, const uint8_t *Bytes,
const unsigned BytesSize, uint64_t Address)
static DecodeStatus getInstruction(MCInst *MI, uint64_t *Size,
const uint8_t *Bytes, unsigned BytesSize,
uint64_t Address)
{
uint32_t Insn;
DecodeStatus Result;

bool IsLittleEndian = MI->csh->mode & CS_MODE_BIG_ENDIAN;
Result = readInstruction24(Bytes, BytesSize, Size, &Insn,
IsLittleEndian);
Result = readInstruction24(Bytes, BytesSize, Size, &Insn);
if (Result == MCDisassembler_Fail)
return MCDisassembler_Fail;
// LLVM_DEBUG(dbgs() << "Trying Xtensa 24-bit instruction table :\n");
Result = decodeInstruction(DecoderTable24, MI, Insn, Address, NULL);
return Result;
}

DecodeStatus Xtensa_LLVM_getInstruction(MCInst *MI, uint16_t *size16,
const uint8_t *Bytes,
unsigned BytesSize, uint64_t Address)
{
uint64_t size64;
DecodeStatus status =
getInstruction(MI, &size64, Bytes, BytesSize, Address);
assert(size64 < 0xffff);
*size16 = size64;
return status == MCDisassembler_Success;
}
5 changes: 3 additions & 2 deletions arch/Xtensa/XtensaDisassembler.h
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Expand Up @@ -3,7 +3,8 @@

#include "../../MCDisassembler.h"

DecodeStatus getInstruction(MCInst *MI, uint64_t *Size, const uint8_t *Bytes,
unsigned BytesSize, uint64_t Address);
DecodeStatus Xtensa_LLVM_getInstruction(MCInst *MI, uint16_t *Size,
const uint8_t *Bytes,
unsigned BytesSize, uint64_t Address);

#endif
14 changes: 0 additions & 14 deletions arch/Xtensa/XtensaGenCSFeatureEnum.inc
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This file was deleted.

114 changes: 30 additions & 84 deletions arch/Xtensa/XtensaInstPrinter.c
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Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,7 @@
static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O);
static const char *getRegisterName(unsigned RegNo);

void printOperand_(const MCOperand *MC, SStream *O)
static void printOperand_(const MCOperand *MC, SStream *O)
{
if (MCOperand_isReg(MC))
SStream_concat0(O, getRegisterName(MCOperand_getReg(MC)));
Expand All @@ -54,25 +54,20 @@ void printOperand_(const MCOperand *MC, SStream *O)
report_fatal_error("Invalid operand");
}

void printRegName(SStream *O, MCRegister Reg)
{
SStream_concat0(O, getRegisterName(Reg));
}

void printOperand(MCInst *MI, int OpNum, SStream *O)
static void printOperand(MCInst *MI, int OpNum, SStream *O)
{
printOperand_(MCInst_getOperand(MI, (OpNum)), O);
}

void printMemOperand(MCInst *MI, int OpNum, SStream *OS)
static inline void printMemOperand(MCInst *MI, int OpNum, SStream *OS)
{
SStream_concat0(OS, getRegisterName(MCOperand_getReg(
MCInst_getOperand(MI, (OpNum)))));
SStream_concat0(OS, ", ");
printOperand(MI, OpNum + 1, OS);
}

void printBranchTarget(MCInst *MI, int OpNum, SStream *OS)
static inline void printBranchTarget(MCInst *MI, int OpNum, SStream *OS)
{
MCOperand *MC = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
Expand All @@ -82,12 +77,11 @@ void printBranchTarget(MCInst *MI, int OpNum, SStream *OS)
SStream_concat0(OS, "+");

printInt64(OS, Val);
}
else
} else
assert(0 && "Invalid operand");
}

void printJumpTarget(MCInst *MI, int OpNum, SStream *OS)
static inline void printJumpTarget(MCInst *MI, int OpNum, SStream *OS)
{
MCOperand *MC = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MC)) {
Expand All @@ -97,13 +91,12 @@ void printJumpTarget(MCInst *MI, int OpNum, SStream *OS)
SStream_concat0(OS, "+");

printInt64(OS, Val);
}
else
} else
assert(0 && "Invalid operand");
;
}

void printCallOperand(MCInst *MI, int OpNum, SStream *OS)
static inline void printCallOperand(MCInst *MI, int OpNum, SStream *OS)
{
MCOperand *MC = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MC)) {
Expand All @@ -113,12 +106,11 @@ void printCallOperand(MCInst *MI, int OpNum, SStream *OS)
SStream_concat0(OS, "+");

printInt64(OS, Val);
}
else
} else
assert(0 && "Invalid operand");
}

void printL32RTarget(MCInst *MI, int OpNum, SStream *O)
static inline void printL32RTarget(MCInst *MI, int OpNum, SStream *O)
{
MCOperand *MC = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MC)) {
Expand All @@ -130,12 +122,11 @@ void printL32RTarget(MCInst *MI, int OpNum, SStream *O)
Value += ((InstrOff + 0x3) & 0x4) - InstrOff;
SStream_concat0(O, ". ");
printInt64(O, Value);
}
else
} else
assert(0 && "Invalid operand");
}

void printImm8_AsmOperand(MCInst *MI, int OpNum, SStream *O)
static inline void printImm8_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
Expand All @@ -147,29 +138,7 @@ void printImm8_AsmOperand(MCInst *MI, int OpNum, SStream *O)
}
}

void printImm8_sh8_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));

printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}

void printImm12_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));

printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}

void printImm12m_AsmOperand(MCInst *MI, int OpNum, SStream *O)
static inline void printImm8_sh8_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
Expand All @@ -180,7 +149,7 @@ void printImm12m_AsmOperand(MCInst *MI, int OpNum, SStream *O)
printOperand(MI, OpNum, O);
}

void printUimm4_AsmOperand(MCInst *MI, int OpNum, SStream *O)
static inline void printImm12m_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
Expand All @@ -191,7 +160,7 @@ void printUimm4_AsmOperand(MCInst *MI, int OpNum, SStream *O)
printOperand(MI, OpNum, O);
}

void printUimm5_AsmOperand(MCInst *MI, int OpNum, SStream *O)
static inline void printUimm4_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
Expand All @@ -202,7 +171,7 @@ void printUimm5_AsmOperand(MCInst *MI, int OpNum, SStream *O)
printOperand(MI, OpNum, O);
}

void printShimm1_31_AsmOperand(MCInst *MI, int OpNum, SStream *O)
static inline void printUimm5_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
Expand All @@ -213,7 +182,7 @@ void printShimm1_31_AsmOperand(MCInst *MI, int OpNum, SStream *O)
printOperand(MI, OpNum, O);
}

void printImm1_16_AsmOperand(MCInst *MI, int OpNum, SStream *O)
static inline void printShimm1_31_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
Expand All @@ -224,7 +193,7 @@ void printImm1_16_AsmOperand(MCInst *MI, int OpNum, SStream *O)
printOperand(MI, OpNum, O);
}

void printOffset8m8_AsmOperand(MCInst *MI, int OpNum, SStream *O)
static inline void printImm1_16_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
Expand All @@ -235,40 +204,7 @@ void printOffset8m8_AsmOperand(MCInst *MI, int OpNum, SStream *O)
printOperand(MI, OpNum, O);
}

void printOffset8m16_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));

printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}

void printOffset8m32_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));

printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}

void printOffset4m32_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));

printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}

void printB4const_AsmOperand(MCInst *MI, int OpNum, SStream *O)
static inline void printB4const_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
Expand Down Expand Up @@ -300,7 +236,7 @@ void printB4const_AsmOperand(MCInst *MI, int OpNum, SStream *O)
printOperand(MI, OpNum, O);
}

void printB4constu_AsmOperand(MCInst *MI, int OpNum, SStream *O)
static inline void printB4constu_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
Expand Down Expand Up @@ -333,3 +269,13 @@ void printB4constu_AsmOperand(MCInst *MI, int OpNum, SStream *O)
}

#include "XtensaGenAsmWriter.inc"

const char *Xtensa_LLVM_getRegisterName(unsigned RegNo)
{
return getRegisterName(RegNo);
}

void Xtensa_LLVM_printInstruction(MCInst *MI, uint64_t Address, SStream *O)
{
printInstruction(MI, Address, O);
}
29 changes: 2 additions & 27 deletions arch/Xtensa/XtensaInstPrinter.h
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Original file line number Diff line number Diff line change
Expand Up @@ -39,32 +39,7 @@

#include "priv.h"

// Automatically generated by tblgen.
void printInstruction(MCInst *MI, uint64_t Address, SStream *O);
// Override MCInstPrinter.
void printRegName(SStream *O, MCRegister Reg);
// Print various types of operand.
void printOperand(MCInst *MI, int OpNum, SStream *O);
void printMemOperand(MCInst *MI, int OpNUm, SStream *O);
void printBranchTarget(MCInst *MI, int OpNum, SStream *O);
void printJumpTarget(MCInst *MI, int OpNum, SStream *O);
void printCallOperand(MCInst *MI, int OpNum, SStream *O);
void printL32RTarget(MCInst *MI, int OpNum, SStream *O);
void printImm8_AsmOperand(MCInst *MI, int OpNum, SStream *O);
void printImm8_sh8_AsmOperand(MCInst *MI, int OpNum, SStream *O);
void printImm12_AsmOperand(MCInst *MI, int OpNum, SStream *O);
void printImm12m_AsmOperand(MCInst *MI, int OpNum, SStream *O);
void printUimm4_AsmOperand(MCInst *MI, int OpNum, SStream *O);
void printUimm5_AsmOperand(MCInst *MI, int OpNum, SStream *O);
void printShimm1_31_AsmOperand(MCInst *MI, int OpNum, SStream *O);
void printImm1_16_AsmOperand(MCInst *MI, int OpNum, SStream *O);
void printOffset8m8_AsmOperand(MCInst *MI, int OpNum, SStream *O);
void printOffset8m16_AsmOperand(MCInst *MI, int OpNum, SStream *O);
void printOffset8m32_AsmOperand(MCInst *MI, int OpNum, SStream *O);
void printOffset4m32_AsmOperand(MCInst *MI, int OpNum, SStream *O);
void printB4const_AsmOperand(MCInst *MI, int OpNum, SStream *O);
void printB4constu_AsmOperand(MCInst *MI, int OpNum, SStream *O);
;
// end namespace llvm
const char *Xtensa_LLVM_getRegisterName(unsigned RegNo);
void Xtensa_LLVM_printInstruction(MCInst *MI, uint64_t Address, SStream *O);

#endif /* LLVM_LIB_TARGET_XTENSA_MCTARGETDESC_XTENSAINSTPRINTER_H */
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