Fix Branch Target

imbillow · Oct 11, 2024 · 2cdb9e3 · 2cdb9e3
1 parent 5bd05e3
commit 2cdb9e3
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/arch/Xtensa/XtensaDisassembler.c b/arch/Xtensa/XtensaDisassembler.c
@@ -90,7 +90,7 @@ static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
 {
 	//	return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
 	//					     Offset, /*OpSize=*/0, InstSize);
-	return true;
+	return false;
 }
 
 static DecodeStatus decodeCallOperand(MCInst *Inst, uint64_t Imm,

diff --git a/arch/Xtensa/XtensaMapping.c b/arch/Xtensa/XtensaMapping.c
@@ -195,8 +195,8 @@ void Xtensa_add_cs_detail(MCInst *MI, xtensa_op_group op_group, va_list args)
 	case XTENSA_OP_GROUP_CALLOPERAND: {
 		int64_t val =
 			MCOperand_getImm(MCInst_getOperand(MI, op_num)) + 4;
-		xop->type = XTENSA_OP_MEM_IMM;
-		xop->mem.base = (int32_t)val;
+		xop->type = XTENSA_OP_IMM;
+		xop->imm = (int32_t)val;
 	} break;
 	case XTENSA_OP_GROUP_L32RTARGET: {
 		int64_t Value =