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stm32f411re added
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@ilg-ul
ilg-ul committed Aug 4, 2015
1 parent 886e28f commit d230e49
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Showing 8 changed files with 1,372 additions and 276 deletions.
6 changes: 2 additions & 4 deletions hw/arm/stm32-mcu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -268,10 +268,8 @@ static void stm32_mcu_memory_regions_create_callback(DeviceState *dev)
static Property stm32_mcu_properties[] = {
DEFINE_PROP_STM32CAPABILITIES_PTR("stm32-capabilities",
STM32MCUState, param_capabilities),
DEFINE_PROP_UINT32("hse-freq-hz", STM32MCUState, hse_freq_hz,
DEFAULT_HSE_FREQ_HZ),
DEFINE_PROP_UINT32("lse-freq-hz", STM32MCUState, lse_freq_hz,
DEFAULT_RTC_FREQ_HZ),
DEFINE_PROP_UINT32("hse-freq-hz", STM32MCUState, hse_freq_hz, 0),
DEFINE_PROP_UINT32("lse-freq-hz", STM32MCUState, lse_freq_hz, 0),
DEFINE_PROP_END_OF_LIST(), /**/
};

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85 changes: 78 additions & 7 deletions hw/arm/stm32-mcus.c
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Original file line number Diff line number Diff line change
Expand Up @@ -262,7 +262,7 @@ static const STM32Capabilities stm32f405xx = {
.is_01_57_xx = true },

.hsi_freq_hz = 16000000,
//.lsi_freq_hz = 40000,
.lsi_freq_hz = 32000,
.has_rcc = true,
.has_pwr = true,
.has_rtc = true,
Expand Down Expand Up @@ -346,7 +346,7 @@ static const STM32Capabilities stm32f407xx = {
.is_01_57_xx = true },

.hsi_freq_hz = 16000000,
//.lsi_freq_hz = 40000,
.lsi_freq_hz = 32000,
.has_rcc = true,
.has_pwr = true,
.has_rtc = true,
Expand Down Expand Up @@ -424,14 +424,79 @@ static const STM32Capabilities stm32f407xx = {
.has_dac1 = true, /* 12-bits */
.has_dac2 = true, };

static const STM32Capabilities stm32f411xx = {

.family = STM32_FAMILY_F4,
.f4 = {
.is11xx = true },

.hsi_freq_hz = 16000000,
.lsi_freq_hz = 32000,
.has_rcc = true,
.has_pwr = true,
.has_rtc = true,
.num_back_bytes = 80,
.has_periph_bitband = true,

.has_crc = true,
.has_dma1 = true,
.num_dma1 = 8,
.has_dma2 = true,
.num_dma2 = 8,
//.has_fsmc = true,
.has_exti = true,
.num_exti = 21,

.has_ac_tim1 = true,
.has_gp_tim2 = true,
.has_gp_tim3 = true,
.has_gp_tim4 = true,
.has_gp_tim5 = true,
.has_gp_tim9 = true,
.has_gp_tim10 = true,
.has_gp_tim11 = true,

.has_iwdg = true,
.has_wwdg = true,
.has_i2c1 = true,
.has_i2c2 = true,
.has_i2c3 = true,
.has_usart1 = true,
.has_usart2 = true,
.has_usart6 = true,
.has_spi1 = true,
.has_spi2 = true,
.has_spi3 = true,
.has_spi4 = true,
.has_spi5 = true,
.has_i2s1 = true,
.has_i2s2 = true,
.has_plli2s = true,
.has_sdio = true,

.has_usb_otg_fs = true,

.has_gpioa = true,
.has_gpiob = true,
.has_gpioc = true,
.has_gpiod = true,
.has_gpioe = true,

.has_gpioh = true, // TODO: only H0 & H1 are present

.has_adc1 = true, /* 12-bits, 16 channels */
.has_ts = true, /* ADC1_IN16 */

};

static const STM32Capabilities stm32f429xx = {

.family = STM32_FAMILY_F4,
.f4 = {
.is_23_xxx = true },

.hsi_freq_hz = 16000000,
//.lsi_freq_hz = 40000,
.lsi_freq_hz = 32000,
.has_rcc = true,
.has_pwr = true,
.has_rtc = true,
Expand Down Expand Up @@ -592,6 +657,14 @@ static const CortexMCoreCapabilities stm32f4_23_xxx_core = {
.nvic_bits = 4, /**/
};

static const CortexMCoreCapabilities stm32f411xx_core = {
.cpu_model = "cortex-m4", /* TODO: make 4f when possible */
.has_mpu = true,
.has_itm = true,
.num_irq = 62,
.nvic_bits = 4, /**/
};

/* ------------------------------------------------------------------------- */

static const STM32PartInfo stm32_mcus[] = {
Expand Down Expand Up @@ -692,16 +765,14 @@ static const STM32PartInfo stm32_mcus[] = {
.core = &stm32f4_01_57_xx_core, },
.stm32 = &stm32f407xx /**/
},
#if 0
{
.name = TYPE_STM32F411RE,
.cortexm = {
.flash_size_kb = 512,
.sram_size_kb = 128, /* No CCM */
.core = &stm32f4xx_core, /* TODO: Add .stm32 */
}, /**/
.core = &stm32f411xx_core, },
.stm32 = &stm32f411xx /**/
},
#endif
{
.name = TYPE_STM32F429ZI,
.cortexm = {
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5 changes: 4 additions & 1 deletion hw/gpio/stm32-gpio.c
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Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,9 @@
* STM32F405xx/07xx, STM32F415xx/17xx, STM32F42xxx and STM32F43xxx
* advanced ARM-based 32-bit MCUs"
*
* - Doc ID 026448 Rev 1, "ST RM0383 Reference manual,
* STM32F411xC/E advanced ARM-based 32-bit MCUs"
*
* All STM32 reference manuals available from:
* http://www.st.com/stonline/stappl/resourceSelector/\
* app?page=fullResourceSelector&doctype=reference_manual&FamilyID=141
Expand Down Expand Up @@ -341,7 +344,7 @@ static void stm32f1_gpio_update_dir_mask(STM32GPIOState *state, int index)

/* ===== F4 ================================================================ */

/* STM32F4[01][57]xx, STM32F4[23]xxx */
/* STM32F4[01][57]xx, STM32F4[23]xxx, STM32F411xx */

uint32_t stm32f4_gpio_get_config_bits(uint32_t value, uint32_t bit);
static void stm32f4_gpio_update_dir_mask(STM32GPIOState *state);
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70 changes: 70 additions & 0 deletions hw/misc/stm32-flash.c
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Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,9 @@
* STM32F405xx/07xx, STM32F415xx/17xx, STM32F42xxx and STM32F43xxx
* advanced ARM-based 32-bit MCUs"
*
* - Doc ID 026448 Rev 1, "ST RM0383 Reference manual,
* STM32F411xC/E advanced ARM-based 32-bit MCUs"
*
* All STM32 reference manuals available from:
* http://www.st.com/stonline/stappl/resourceSelector/\
* app?page=fullResourceSelector&doctype=reference_manual&FamilyID=141
Expand Down Expand Up @@ -307,6 +310,71 @@ static void stm32f4_01_57_xx_flash_create_objects(Object *obj)
peripheral_new_with_info(obj, NULL, &stm32f4_01_57_xx_flash_info);
}

static PeripheralInfo stm32f411xx_flash_info = {
.desc = "Reset and clock control (RCC)",

.registers = (PeripheralRegisterInfo[] ) {
{
.desc = "Flash access control register (FLASH_ACR)",
.name = "acr",
.offset_bytes = 0x00,
.reset_value = 0x00000030,
.bitfields = (RegisterBitfieldInfo[] ) {
{
.name = "latency",
.first_bit = 0,
.width_bits = 4, },
{
.name = "prften",
.desc = "Prefetch enable",
.first_bit = 8, },
{
.name = "icen",
.desc = "Prefetch enable",
.first_bit = 9, },
{
.name = "dcen",
.desc = "Data cache enable",
.first_bit = 10, },
{
.name = "icrst",
.desc = "Instruction cache reset",
.first_bit = 11,
.rw_mode = REGISTER_RW_MODE_READ, },
{
.name = "dcrst",
.desc = "Data cache reset",
.first_bit = 12, },
{ }, /**/
} , /**/
},
/* Very schematic, functional read after write only. */
{
.name = "keyr",
.offset_bytes = 0x04, },
{
.name = "optkeyr",
.offset_bytes = 0x08, },
{
.name = "sr",
.offset_bytes = 0x0C, },
{
.name = "cr",
.offset_bytes = 0x10, },
{
.name = "optcr",
.offset_bytes = 0x14, },
{ }, /**/
} , /**/
};

static void stm32f411xx_flash_create_objects(Object *obj)
{
//STM32FlashState *state = STM32_FLASH_STATE(obj);

peripheral_new_with_info(obj, NULL, &stm32f411xx_flash_info);
}

static PeripheralInfo stm32f4_23_xxx_flash_info = {
.desc = "Reset and clock control (RCC)",

Expand Down Expand Up @@ -473,6 +541,8 @@ static void stm32_flash_realize_callback(DeviceState *dev, Error **errp)

if (capabilities->f4.is_01_57_xx) {
stm32f4_01_57_xx_flash_create_objects(obj);
} else if (capabilities->f4.is11xx) {
stm32f411xx_flash_create_objects(obj);
} else if (capabilities->f4.is_23_xxx) {
stm32f4_23_xxx_flash_create_objects(obj);
}
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