SLM control by FPGA

• Test FIFO write: assuming that the image is a horizontal strip with vertical position controlled by SW
• VGA display control syncronization (be noted that the two SYNC signals might change polarity (active high (current) -> active low) if SLM uses regular VGA convention)
• Test FIFO write: use a pattern with variations in each of its horizontal lines. (this checks if the horizontal sync is correct)
• Write vertical strip patterns into memory (64MB)
• Memory to FIFO with the id of line_to_load and the id of image_to_load
• JTAG-UART communication for downloading images to memory (7-segment indicators for loading taking place)
• JTAG-UART communication for experimental commands
• sequencer according the communicated information

Usage

Compilation

1. Open Qsys inside Quartus Prime and generate codes.
2. Hit Generate HDL codes.
3. Start "Start Compilation (CTRL+L)"

Burning onto FPGA

1. Open "Programmer"
2. If it is a empty one, click Auto Detect and select 5CSEMA5.
3. Click Add File and choose output_files/SLMCtrl.sof
4. Click Hardware Setup and select DE1-SoC
5. Click Start

Burning onto the Flash drive next to FPGA so that FPGA is loaded at power-up everytime 0. (Chapter 8 of DE1-SoC user manual) (please search in google with "DE1 SoC user manual")