sched: replace sync pause with async pause for nxsig_process

Signed-off-by: hujun5 <[email protected]>
hujun260 · Sep 30, 2024 · 0be7806 · 0be7806
1 parent 6111d95
commit 0be7806
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Showing 13 changed files with 115 additions and 398 deletions.
diff --git a/arch/arm/src/armv6-m/arm_schedulesigaction.c b/arch/arm/src/armv6-m/arm_schedulesigaction.c
@@ -101,30 +101,6 @@ void up_schedule_sigaction(struct tcb_s *tcb)
     }
   else
     {
-      /* CASE 2:  The task that needs to receive the signal is running.
-       * This could happen if the task is running on another CPU OR if
-       * we are in an interrupt handler and the task is running on this
-       * CPU.  In the former case, we will have to PAUSE the other CPU
-       * first.  But in either case, we will have to modify the return
-       * state as well as the state in the TCB.
-       */
-
-      /* If we signaling a task running on the other CPU, we have
-       * to PAUSE the other CPU.
-       */
-
-#ifdef CONFIG_SMP
-      int cpu = tcb->cpu;
-      int me  = this_cpu();
-
-      if (cpu != me && tcb->task_state == TSTATE_TASK_RUNNING)
-        {
-          /* Pause the CPU */
-
-          up_cpu_pause(cpu);
-        }
-#endif
-
       /* Save the return PC, CPSR and either the BASEPRI or PRIMASK
        * registers (and perhaps also the LR).  These will be restored
        * by the signal trampoline after the signal has been delivered.
@@ -160,14 +136,5 @@ void up_schedule_sigaction(struct tcb_s *tcb)
       tcb->xcp.regs[REG_EXC_RETURN] = EXC_RETURN_THREAD;
       tcb->xcp.regs[REG_CONTROL]    = getcontrol() & ~CONTROL_NPRIV;
 #endif
-
-#ifdef CONFIG_SMP
-      /* RESUME the other CPU if it was PAUSED */
-
-      if (cpu != me && tcb->task_state == TSTATE_TASK_RUNNING)
-        {
-          up_cpu_resume(cpu);
-        }
-#endif
     }
 }
diff --git a/arch/arm/src/armv7-a/arm_schedulesigaction.c b/arch/arm/src/armv7-a/arm_schedulesigaction.c
@@ -99,30 +99,6 @@ void up_schedule_sigaction(struct tcb_s *tcb)
     }
   else
     {
-      /* CASE 2:  The task that needs to receive the signal is running.
-       * This could happen if the task is running on another CPU OR if
-       * we are in an interrupt handler and the task is running on this
-       * CPU.  In the former case, we will have to PAUSE the other CPU
-       * first.  But in either case, we will have to modify the return
-       * state as well as the state in the TCB.
-       */
-
-      /* If we signaling a task running on the other CPU, we have
-       * to PAUSE the other CPU.
-       */
-
-#ifdef CONFIG_SMP
-      int cpu = tcb->cpu;
-      int me  = this_cpu();
-
-      if (cpu != me && tcb->task_state == TSTATE_TASK_RUNNING)
-        {
-          /* Pause the CPU */
-
-          up_cpu_pause(cpu);
-        }
-#endif
-
       /* Save the return lr and cpsr and one scratch register.  These
        * will be restored by the signal trampoline after the signals
        * have been delivered.
@@ -154,14 +130,5 @@ void up_schedule_sigaction(struct tcb_s *tcb)
 #ifdef CONFIG_ARM_THUMB
       tcb->xcp.regs[REG_CPSR] |= PSR_T_BIT;
 #endif
-
-#ifdef CONFIG_SMP
-      /* RESUME the other CPU if it was PAUSED */
-
-      if (cpu != me && tcb->task_state == TSTATE_TASK_RUNNING)
-        {
-          up_cpu_resume(cpu);
-        }
-#endif
     }
 }
diff --git a/arch/arm/src/armv7-m/arm_schedulesigaction.c b/arch/arm/src/armv7-m/arm_schedulesigaction.c
@@ -102,30 +102,6 @@ void up_schedule_sigaction(struct tcb_s *tcb)
     }
   else
     {
-      /* CASE 2:  The task that needs to receive the signal is running.
-       * This could happen if the task is running on another CPU OR if
-       * we are in an interrupt handler and the task is running on this
-       * CPU.  In the former case, we will have to PAUSE the other CPU
-       * first.  But in either case, we will have to modify the return
-       * state as well as the state in the TCB.
-       */
-
-      /* If we signaling a task running on the other CPU, we have
-       * to PAUSE the other CPU.
-       */
-
-#ifdef CONFIG_SMP
-      int cpu = tcb->cpu;
-      int me  = this_cpu();
-
-      if (cpu != me && tcb->task_state == TSTATE_TASK_RUNNING)
-        {
-          /* Pause the CPU */
-
-          up_cpu_pause(cpu);
-        }
-#endif
-
       /* Save the return PC, CPSR and either the BASEPRI or PRIMASK
        * registers (and perhaps also the LR).  These will be restored
        * by the signal trampoline after the signal has been delivered.
@@ -165,14 +141,5 @@ void up_schedule_sigaction(struct tcb_s *tcb)
       tcb->xcp.regs[REG_EXC_RETURN] = EXC_RETURN_THREAD;
       tcb->xcp.regs[REG_CONTROL]    = getcontrol() & ~CONTROL_NPRIV;
 #endif
-
-#ifdef CONFIG_SMP
-      /* RESUME the other CPU if it was PAUSED */
-
-      if (cpu != me && tcb->task_state == TSTATE_TASK_RUNNING)
-        {
-          up_cpu_resume(cpu);
-        }
-#endif
     }
 }
diff --git a/arch/arm/src/armv7-r/arm_schedulesigaction.c b/arch/arm/src/armv7-r/arm_schedulesigaction.c
@@ -97,22 +97,6 @@ void up_schedule_sigaction(struct tcb_s *tcb)
     }
   else
     {
-      /* If we signaling a task running on the other CPU, we have
-       * to PAUSE the other CPU.
-       */
-
-#ifdef CONFIG_SMP
-      int cpu = tcb->cpu;
-      int me  = this_cpu();
-
-      if (cpu != me && tcb->task_state == TSTATE_TASK_RUNNING)
-        {
-          /* Pause the CPU */
-
-          up_cpu_pause(cpu);
-        }
-#endif
-
       /* Save the return lr and cpsr and one scratch register.  These
        * will be restored by the signal trampoline after the signals
        * have been delivered.
@@ -144,14 +128,5 @@ void up_schedule_sigaction(struct tcb_s *tcb)
 #ifdef CONFIG_ARM_THUMB
       tcb->xcp.regs[REG_CPSR] |= PSR_T_BIT;
 #endif
-
-#ifdef CONFIG_SMP
-      /* RESUME the other CPU if it was PAUSED */
-
-      if (cpu != me && tcb->task_state == TSTATE_TASK_RUNNING)
-        {
-          up_cpu_resume(cpu);
-        }
-#endif
     }
 }
diff --git a/arch/arm/src/armv8-m/arm_schedulesigaction.c b/arch/arm/src/armv8-m/arm_schedulesigaction.c
@@ -102,30 +102,6 @@ void up_schedule_sigaction(struct tcb_s *tcb)
     }
   else
     {
-      /* CASE 2:  The task that needs to receive the signal is running.
-       * This could happen if the task is running on another CPU OR if
-       * we are in an interrupt handler and the task is running on this
-       * CPU.  In the former case, we will have to PAUSE the other CPU
-       * first.  But in either case, we will have to modify the return
-       * state as well as the state in the TCB.
-       */
-
-      /* If we signaling a task running on the other CPU, we have
-       * to PAUSE the other CPU.
-       */
-
-#ifdef CONFIG_SMP
-      int cpu = tcb->cpu;
-      int me  = this_cpu();
-
-      if (cpu != me && tcb->task_state == TSTATE_TASK_RUNNING)
-        {
-          /* Pause the CPU */
-
-          up_cpu_pause(cpu);
-        }
-#endif
-
       /* Save the return PC, CPSR and either the BASEPRI or PRIMASK
        * registers (and perhaps also the LR).  These will be restored
        * by the signal trampoline after the signal has been delivered.
@@ -165,14 +141,5 @@ void up_schedule_sigaction(struct tcb_s *tcb)
       tcb->xcp.regs[REG_EXC_RETURN] = EXC_RETURN_THREAD;
       tcb->xcp.regs[REG_CONTROL]    = getcontrol() & ~CONTROL_NPRIV;
 #endif
-
-#ifdef CONFIG_SMP
-      /* RESUME the other CPU if it was PAUSED */
-
-      if (cpu != me && tcb->task_state == TSTATE_TASK_RUNNING)
-        {
-          up_cpu_resume(cpu);
-        }
-#endif
     }
 }
diff --git a/arch/arm/src/armv8-r/arm_schedulesigaction.c b/arch/arm/src/armv8-r/arm_schedulesigaction.c
@@ -97,22 +97,6 @@ void up_schedule_sigaction(struct tcb_s *tcb)
     }
   else
     {
-      /* If we signaling a task running on the other CPU, we have
-       * to PAUSE the other CPU.
-       */
-
-#ifdef CONFIG_SMP
-      int cpu = tcb->cpu;
-      int me  = this_cpu();
-
-      if (cpu != me && tcb->task_state == TSTATE_TASK_RUNNING)
-        {
-          /* Pause the CPU */
-
-          up_cpu_pause(cpu);
-        }
-#endif
-
       /* Save the return lr and cpsr and one scratch register.  These
        * will be restored by the signal trampoline after the signals
        * have been delivered.
@@ -144,14 +128,5 @@ void up_schedule_sigaction(struct tcb_s *tcb)
 #ifdef CONFIG_ARM_THUMB
       tcb->xcp.regs[REG_CPSR] |= PSR_T_BIT;
 #endif
-
-#ifdef CONFIG_SMP
-      /* RESUME the other CPU if it was PAUSED */
-
-      if (cpu != me && tcb->task_state == TSTATE_TASK_RUNNING)
-        {
-          up_cpu_resume(cpu);
-        }
-#endif
     }
 }
diff --git a/arch/arm64/src/common/arm64_schedulesigaction.c b/arch/arm64/src/common/arm64_schedulesigaction.c
@@ -148,18 +148,6 @@ void up_schedule_sigaction(struct tcb_s *tcb)
     }
   else
     {
-#ifdef CONFIG_SMP
-      int cpu = tcb->cpu;
-      int me  = this_cpu();
-
-      if (cpu != me && tcb->task_state == TSTATE_TASK_RUNNING)
-        {
-          /* Pause the CPU */
-
-          up_cpu_pause(cpu);
-        }
-#endif
-
       /* Save the return lr and cpsr and one scratch register.  These
        * will be restored by the signal trampoline after the signals
        * have been delivered.
@@ -173,14 +161,5 @@ void up_schedule_sigaction(struct tcb_s *tcb)
       /* create signal process context */
 
       arm64_init_signal_process(tcb, NULL);
-
-#ifdef CONFIG_SMP
-      /* RESUME the other CPU if it was PAUSED */
-
-      if (cpu != me && tcb->task_state == TSTATE_TASK_RUNNING)
-        {
-          up_cpu_resume(cpu);
-        }
-#endif
     }
 }
diff --git a/arch/ceva/src/common/ceva_schedulesigaction.c b/arch/ceva/src/common/ceva_schedulesigaction.c
@@ -115,21 +115,6 @@ void up_schedule_sigaction(struct tcb_s *tcb)
 
       else
         {
-#ifdef CONFIG_SMP
-          /* If we signaling a task running on the other CPU, we have
-           * to PAUSE the other CPU.
-           */
-
-          if (cpu != me)
-            {
-              /* Pause the CPU */
-
-              up_cpu_pause(cpu);
-            }
-
-          /* Now tcb on the other CPU can be accessed safely */
-#endif
-
           /* Save the current register context location */
 
           tcb->xcp.saved_regs = up_current_regs();
@@ -155,15 +140,6 @@ void up_schedule_sigaction(struct tcb_s *tcb)
           up_current_regs()[REG_OM] &= ~REG_OM_MASK;
           up_current_regs()[REG_OM] |=  REG_OM_KERNEL;
 #endif
-
-#ifdef CONFIG_SMP
-          /* RESUME the other CPU if it was PAUSED */
-
-          if (cpu != me)
-            {
-              up_cpu_resume(cpu);
-            }
-#endif
         }
     }
 

diff --git a/arch/risc-v/src/common/riscv_schedulesigaction.c b/arch/risc-v/src/common/riscv_schedulesigaction.c
@@ -100,18 +100,6 @@ void up_schedule_sigaction(struct tcb_s *tcb)
     }
   else
     {
-#ifdef CONFIG_SMP
-      int cpu = tcb->cpu;
-      int me  = this_cpu();
-
-      if (cpu != me && tcb->task_state == TSTATE_TASK_RUNNING)
-        {
-          /* Pause the CPU */
-
-          up_cpu_pause(cpu);
-        }
-#endif
-
       /* Save the return EPC and STATUS registers.  These will be
        * by the signal trampoline after the signal has been delivered.
        */
@@ -148,13 +136,5 @@ void up_schedule_sigaction(struct tcb_s *tcb)
 #endif
 
       tcb->xcp.regs[REG_INT_CTX] = int_ctx;
-#ifdef CONFIG_SMP
-      /* RESUME the other CPU if it was PAUSED */
-
-      if (cpu != me && tcb->task_state == TSTATE_TASK_RUNNING)
-        {
-          up_cpu_resume(cpu);
-        }
-#endif
     }
 }