arch: rename xxxx_pause.c to xxxx_smpcall.c

Signed-off-by: hujun5 <[email protected]>

arch/arm/include/cxd56xx/irq.h

@@ -158,7 +158,7 @@
 #define CXD56_IRQ_SPH13         (CXD56_IRQ_EXTINT+93)  /* SPH13 IRQ number */
 #define CXD56_IRQ_SPH14         (CXD56_IRQ_EXTINT+94)  /* SPH14 IRQ number */
 #define CXD56_IRQ_SPH15         (CXD56_IRQ_EXTINT+95)  /* SPH15 IRQ number */
-#define CXD56_IRQ_SW_INT        (CXD56_IRQ_EXTINT+96)  /* SW_INT IRQ number */
+#define CXD56_IRQ_SMP_CALL      (CXD56_IRQ_EXTINT+96)  /* SMP_CALL IRQ number */
 #define CXD56_IRQ_TIMER0        (CXD56_IRQ_EXTINT+97)  /* TIMER0 IRQ number */
 #define CXD56_IRQ_TIMER1        (CXD56_IRQ_EXTINT+98)  /* TIMER1 IRQ number */
 #define CXD56_IRQ_TIMER2        (CXD56_IRQ_EXTINT+99)  /* TIMER2 IRQ number */

arch/arm/include/lc823450/irq.h

@@ -59,11 +59,11 @@
 #define LC823450_IRQ_INTERRUPTS    (16) /* Vector number of the first external interrupt */
 
 #define LC823450_IRQ_CTXM3_00       (LC823450_IRQ_INTERRUPTS+0)   /* 16: CortexM3_00 interrupt */
-#define LC823450_IRQ_CTXM3_01       (LC823450_IRQ_INTERRUPTS+1)   /* 17: CortexM3_01 interrupt */
+#define LC823450_IRQ_SMP_CALL_01    (LC823450_IRQ_INTERRUPTS+1)   /* 17: CortexM3_01 interrupt */
 #define LC823450_IRQ_CTXM3_02       (LC823450_IRQ_INTERRUPTS+2)   /* 18: CortexM3_02 interrupt */
 #define LC823450_IRQ_CTXM3_03       (LC823450_IRQ_INTERRUPTS+3)   /* 19: CortexM3_03 interrupt */
 #define LC823450_IRQ_CTXM3_10       (LC823450_IRQ_INTERRUPTS+4)   /* 20: CortexM3_00 interrupt */
-#define LC823450_IRQ_CTXM3_11       (LC823450_IRQ_INTERRUPTS+5)   /* 21: CortexM3_01 interrupt */
+#define LC823450_IRQ_SMP_CALL_11    (LC823450_IRQ_INTERRUPTS+5)   /* 21: CortexM3_01 interrupt */
 #define LC823450_IRQ_CTXM3_12       (LC823450_IRQ_INTERRUPTS+6)   /* 22: CortexM3_02 interrupt */
 #define LC823450_IRQ_CTXM3_13       (LC823450_IRQ_INTERRUPTS+7)   /* 23: CortexM3_03 interrupt */
 #define LC823450_IRQ_LPDSP0         (LC823450_IRQ_INTERRUPTS+8)   /* 24: LPDSP0 interrupt */

arch/arm/include/rp2040/irq.h

@@ -75,8 +75,8 @@
 #define RP2040_DMA_IRQ_1      (RP2040_IRQ_EXTINT+12)
 #define RP2040_IO_IRQ_BANK0   (RP2040_IRQ_EXTINT+13)
 #define RP2040_IO_IRQ_QSPI    (RP2040_IRQ_EXTINT+14)
-#define RP2040_SIO_IRQ_PROC0  (RP2040_IRQ_EXTINT+15)
-#define RP2040_SIO_IRQ_PROC1  (RP2040_IRQ_EXTINT+16)
+#define RP2040_SMP_CALL_PROC0 (RP2040_IRQ_EXTINT+15)
+#define RP2040_SMP_CALL_PROC1 (RP2040_IRQ_EXTINT+16)
 #define RP2040_CLOCKS_IRQ     (RP2040_IRQ_EXTINT+17)
 #define RP2040_SPI0_IRQ       (RP2040_IRQ_EXTINT+18)
 #define RP2040_SPI1_IRQ       (RP2040_IRQ_EXTINT+19)

arch/arm/include/sam34/sam4cm_irq.h

@@ -114,15 +114,15 @@
 #define SAM_IRQ_TC5          (SAM_IRQ_EXTINT+SAM_PID_TC5)         /* PID 28: Timer Counter 5 */
 #define SAM_IRQ_ADC          (SAM_IRQ_EXTINT+SAM_PID_ADC)         /* PID 29: Analog To Digital Converter */
 #define SAM_IRQ_ARM          (SAM_IRQ_EXTINT+SAM_PID_ARM)         /* PID 30: FPU signals (only on CM4P1 core): FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */
-#define SAM_IRQ_IPC0         (SAM_IRQ_EXTINT+SAM_PID_IPC0)        /* PID 31: Interprocessor communication 0 */
+#define SAM_IRQ_SMP_CALL0    (SAM_IRQ_EXTINT+SAM_PID_IPC0)        /* PID 31: Interprocessor communication 0 */
 #define SAM_IRQ_SLCDC        (SAM_IRQ_EXTINT+SAM_PID_SLCDC)       /* PID 32: Segment LCD Controller */
 #define SAM_IRQ_TRNG         (SAM_IRQ_EXTINT+SAM_PID_TRNG)        /* PID 33: True Random Generator */
 #define SAM_IRQ_ICM          (SAM_IRQ_EXTINT+SAM_PID_ICM)         /* PID 34: Integrity Check Module */
 #define SAM_IRQ_CPKCC        (SAM_IRQ_EXTINT+SAM_PID_CPKCC)       /* PID 35: Classical Public Key Cryptography Controller */
 #define SAM_IRQ_AES          (SAM_IRQ_EXTINT+SAM_PID_AES)         /* PID 36: Advanced Enhanced Standard */
 #define SAM_IRQ_PIOC         (SAM_IRQ_EXTINT+SAM_PID_PIOC)        /* PID 37: Parallel I/O Controller C */
 #define SAM_IRQ_UART1        (SAM_IRQ_EXTINT+SAM_PID_UART1)       /* PID 38: Universal Asynchronous Receiver Transmitter 1 */
-#define SAM_IRQ_IPC1         (SAM_IRQ_EXTINT+SAM_PID_IPC1)        /* PID 39: Interprocessor communication 1 */
+#define SAM_IRQ_SMP_CALL1    (SAM_IRQ_EXTINT+SAM_PID_IPC1)        /* PID 39: Interprocessor communication 1 */
 #define SAM_IRQ_RESERVED_40  (SAM_IRQ_EXTINT+SAM_PID_RESERVED_40) /* PID 40: Reserved */
 #define SAM_IRQ_PWM          (SAM_IRQ_EXTINT+SAM_PID_PWM)         /* PID 41: Pulse Width Modulation */
 #define SAM_IRQ_SRAM         (SAM_IRQ_EXTINT+SAM_PID_SRAM)        /* PID 42: SRAM1 (I/D Code bus of CM4P1), SRAM2 (Systembus of CM4P1) */

arch/arm/src/armv7-a/CMakeLists.txt

@@ -109,7 +109,7 @@ if(CONFIG_ARCH_FPU)
 endif()
 
 if(CONFIG_SMP)
-  list(APPEND SRCS arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c arm_scu.c)
+  list(APPEND SRCS arm_cpustart.c arm_smpcall.c arm_cpuidlestack.c arm_scu.c)
 endif()
 
 if(CONFIG_ARCH_HAVE_PSCI)

arch/arm/src/armv7-a/Make.defs

@@ -94,7 +94,7 @@ ifeq ($(CONFIG_ARCH_FPU),y)
 endif
 
 ifeq ($(CONFIG_SMP),y)
-  CMN_CSRCS += arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c
+  CMN_CSRCS += arm_cpustart.c arm_smpcall.c arm_cpuidlestack.c
   CMN_CSRCS += arm_scu.c
 endif
 

arch/arm/src/armv7-a/arm_gicv2.c

@@ -219,9 +219,8 @@ void arm_gic0_initialize(void)
   /* Attach SGI interrupt handlers. This attaches the handler to all CPUs. */
 
   DEBUGVERIFY(irq_attach(GIC_SMP_CPUSTART, arm_start_handler, NULL));
-  DEBUGVERIFY(irq_attach(GIC_SMP_CPUPAUSE_ASYNC,
-                         arm_pause_async_handler, NULL));
-  DEBUGVERIFY(irq_attach(GIC_SMP_CPUCALL, nxsched_smp_call_handler, NULL));
+  DEBUGVERIFY(irq_attach(GIC_SMP_SCHED, arm_smp_sched_handler, NULL));
+  DEBUGVERIFY(irq_attach(GIC_SMP_CALL, nxsched_smp_call_handler, NULL));
 #endif
 
   arm_gic_dump("Exit arm_gic0_initialize", true, 0);
@@ -754,27 +753,6 @@ void arm_cpu_sgi(int sgi, unsigned int cpuset)
   putreg32(regval, GIC_ICDSGIR);
 }
 
-#ifdef CONFIG_SMP
-/****************************************************************************
- * Name: up_send_smp_call
- *
- * Description:
- *   Send smp call to target cpu.
- *
- * Input Parameters:
- *   cpuset - The set of CPUs to receive the SGI.
- *
- * Returned Value:
- *   None.
- *
- ****************************************************************************/
-
-void up_send_smp_call(cpu_set_t cpuset)
-{
-  up_trigger_irq(GIC_SMP_CPUCALL, cpuset);
-}
-#endif
-
 /****************************************************************************
  * Name: up_get_legacy_irq
  *

arch/arm/src/armv7-a/arm_cpupause.c → arch/arm/src/armv7-a/arm_smpcall.c

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/armv7-a/arm_cpupause.c
+ * arch/arm/src/armv7-a/arm_smpcall.c
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with
@@ -47,10 +47,10 @@
  ****************************************************************************/
 
 /****************************************************************************
- * Name: arm_pause_async_handler
+ * Name: arm_smp_sched_handler
  *
  * Description:
- *   This is the handler for async pause.
+ *   This is the handler for sched.
  *
  *   1. It saves the current task state at the head of the current assigned
  *      task list.
@@ -66,7 +66,7 @@
  *
  ****************************************************************************/
 
-int arm_pause_async_handler(int irq, void *context, void *arg)
+int arm_smp_sched_handler(int irq, void *context, void *arg)
 {
   int cpu = this_cpu();
 
@@ -75,7 +75,7 @@ int arm_pause_async_handler(int irq, void *context, void *arg)
 }
 
 /****************************************************************************
- * Name: up_cpu_pause_async
+ * Name: up_send_smp_sched
  *
  * Description:
  *   pause task execution on the CPU
@@ -93,11 +93,30 @@ int arm_pause_async_handler(int irq, void *context, void *arg)
  *
  ****************************************************************************/
 
-inline_function int up_cpu_pause_async(int cpu)
+int up_send_smp_sched(int cpu)
 {
-  arm_cpu_sgi(GIC_SMP_CPUPAUSE_ASYNC, (1 << cpu));
+  arm_cpu_sgi(GIC_SMP_SCHED, (1 << cpu));
 
   return OK;
 }
 
+/****************************************************************************
+ * Name: up_send_smp_call
+ *
+ * Description:
+ *   Send smp call to target cpu.
+ *
+ * Input Parameters:
+ *   cpuset - The set of CPUs to receive the SGI.
+ *
+ * Returned Value:
+ *   None.
+ *
+ ****************************************************************************/
+
+void up_send_smp_call(cpu_set_t cpuset)
+{
+  up_trigger_irq(GIC_SMP_CALL, cpuset);
+}
+
 #endif /* CONFIG_SMP */

arch/arm/src/armv7-a/gic.h

@@ -635,14 +635,12 @@
 
 #ifdef CONFIG_ARCH_TRUSTZONE_SECURE
 #  define GIC_SMP_CPUSTART       GIC_IRQ_SGI9
-#  define GIC_SMP_CPUPAUSE       GIC_IRQ_SGI10
-#  define GIC_SMP_CPUCALL        GIC_IRQ_SGI11
-#  define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI12
+#  define GIC_SMP_CALL           GIC_IRQ_SGI10
+#  define GIC_SMP_SCHED          GIC_IRQ_SGI11
 #else
 #  define GIC_SMP_CPUSTART       GIC_IRQ_SGI1
-#  define GIC_SMP_CPUPAUSE       GIC_IRQ_SGI2
-#  define GIC_SMP_CPUCALL        GIC_IRQ_SGI3
-#  define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI4
+#  define GIC_SMP_CALL           GIC_IRQ_SGI2
+#  define GIC_SMP_SCHED          GIC_IRQ_SGI3
 #endif
 
 /****************************************************************************
@@ -836,10 +834,10 @@ int arm_start_handler(int irq, void *context, void *arg);
 #endif
 
 /****************************************************************************
- * Name: arm_pause_async_handler
+ * Name: arm_smp_sched_handler
  *
  * Description:
- *   This is the handler for async pause.
+ *   This is the handler for sched.
  *
  *   1. It saves the current task state at the head of the current assigned
  *      task list.
@@ -856,7 +854,7 @@ int arm_start_handler(int irq, void *context, void *arg);
  ****************************************************************************/
 
 #ifdef CONFIG_SMP
-int arm_pause_async_handler(int irq, void *context, void *arg);
+int arm_smp_sched_handler(int irq, void *context, void *arg);
 #endif
 /****************************************************************************
  * Name: arm_gic_dump

arch/arm/src/armv7-r/CMakeLists.txt

@@ -71,7 +71,7 @@ if(CONFIG_SMP)
     SRCS
     arm_cpuhead.S
     arm_cpustart.c
-    arm_cpupause.c
+    arm_smpcall.c
     arm_cpuidlestack.c
     arm_scu.c)
 endif()

arch/arm/src/armv7-r/Make.defs

@@ -59,6 +59,6 @@ endif
 
 ifeq ($(CONFIG_SMP),y)
   CMN_ASRCS += arm_cpuhead.S
-  CMN_CSRCS += arm_cpustart.c arm_cpupause.c
+  CMN_CSRCS += arm_cpustart.c arm_smpcall.c
   CMN_CSRCS += arm_cpuidlestack.c arm_scu.c
 endif

arch/arm/src/armv7-r/arm_gicv2.c

@@ -160,9 +160,8 @@ void arm_gic0_initialize(void)
   /* Attach SGI interrupt handlers. This attaches the handler to all CPUs. */
 
   DEBUGVERIFY(irq_attach(GIC_SMP_CPUSTART, arm_start_handler, NULL));
-  DEBUGVERIFY(irq_attach(GIC_SMP_CPUPAUSE_ASYNC,
-                         arm_pause_async_handler, NULL));
-  DEBUGVERIFY(irq_attach(GIC_SMP_CPUCALL, nxsched_smp_call_handler, NULL));
+  DEBUGVERIFY(irq_attach(GIC_SMP_SCHED, arm_smp_sched_handler, NULL));
+  DEBUGVERIFY(irq_attach(GIC_SMP_CALL, nxsched_smp_call_handler, NULL));
 #endif
 
   arm_gic_dump("Exit arm_gic0_initialize", true, 0);
@@ -659,24 +658,4 @@ int arm_gic_irq_trigger(int irq, bool edge)
   return -EINVAL;
 }
 
-#  ifdef CONFIG_SMP
-/****************************************************************************
- * Name: up_send_smp_call
- *
- * Description:
- *   Send smp call to target cpu.
- *
- * Input Parameters:
- *   cpuset - The set of CPUs to receive the SGI.
- *
- * Returned Value:
- *   None.
- *
- ****************************************************************************/
-
-void up_send_smp_call(cpu_set_t cpuset)
-{
-  up_trigger_irq(GIC_SMP_CPUCALL, cpuset);
-}
-#  endif
 #endif /* CONFIG_ARMV7R_HAVE_GICv2 */

arch/arm/src/armv7-r/arm_cpupause.c → arch/arm/src/armv7-r/arm_smpcall.c

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/armv7-r/arm_cpupause.c
+ * arch/arm/src/armv7-r/arm_smpcall.c
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with
@@ -47,10 +47,10 @@
  ****************************************************************************/
 
 /****************************************************************************
- * Name: arm_pause_async_handler
+ * Name: arm_smp_sched_handler
  *
  * Description:
- *   This is the handler for async pause.
+ *   This is the handler for sched.
  *
  *   1. It saves the current task state at the head of the current assigned
  *      task list.
@@ -66,7 +66,7 @@
  *
  ****************************************************************************/
 
-int arm_pause_async_handler(int irq, void *context, void *arg)
+int arm_smp_sched_handler(int irq, void *context, void *arg)
 {
   int cpu = this_cpu();
 
@@ -75,7 +75,7 @@ int arm_pause_async_handler(int irq, void *context, void *arg)
 }
 
 /****************************************************************************
- * Name: up_cpu_pause_async
+ * Name: up_send_smp_sched
  *
  * Description:
  *   pause task execution on the CPU
@@ -93,11 +93,30 @@ int arm_pause_async_handler(int irq, void *context, void *arg)
  *
  ****************************************************************************/
 
-inline_function int up_cpu_pause_async(int cpu)
+int up_send_smp_sched(int cpu)
 {
-  arm_cpu_sgi(GIC_SMP_CPUPAUSE_ASYNC, (1 << cpu));
+  arm_cpu_sgi(GIC_SMP_SCHED, (1 << cpu));
 
   return OK;
 }
 
+/****************************************************************************
+ * Name: up_send_smp_call
+ *
+ * Description:
+ *   Send smp call to target cpu.
+ *
+ * Input Parameters:
+ *   cpuset - The set of CPUs to receive the SGI.
+ *
+ * Returned Value:
+ *   None.
+ *
+ ****************************************************************************/
+
+void up_send_smp_call(cpu_set_t cpuset)
+{
+  up_trigger_irq(GIC_SMP_CALL, cpuset);
+}
+
 #endif /* CONFIG_SMP */

arch/arm/src/armv7-r/gic.h

@@ -608,14 +608,12 @@
 
 #ifdef CONFIG_ARCH_TRUSTZONE_SECURE
 #  define GIC_SMP_CPUSTART       GIC_IRQ_SGI9
-#  define GIC_SMP_CPUPAUSE       GIC_IRQ_SGI10
-#  define GIC_SMP_CPUCALL        GIC_IRQ_SGI11
-#  define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI12
+#  define GIC_SMP_CALL           GIC_IRQ_SGI10
+#  define GIC_SMP_SCHED          GIC_IRQ_SGI11
 #else
 #  define GIC_SMP_CPUSTART       GIC_IRQ_SGI1
-#  define GIC_SMP_CPUPAUSE       GIC_IRQ_SGI2
-#  define GIC_SMP_CPUCALL        GIC_IRQ_SGI3
-#  define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI4
+#  define GIC_SMP_CALL           GIC_IRQ_SGI2
+#  define GIC_SMP_SCHED          GIC_IRQ_SGI3
 #endif
 
 /****************************************************************************
@@ -806,10 +804,10 @@ int arm_start_handler(int irq, void *context, void *arg);
 #endif
 
 /****************************************************************************
- * Name: arm_pause_async_handler
+ * Name: arm_smp_sched_handler
  *
  * Description:
- *   This is the handler for async pause.
+ *   This is the handler for sched.
  *
  *   1. It saves the current task state at the head of the current assigned
  *      task list.
@@ -826,7 +824,7 @@ int arm_start_handler(int irq, void *context, void *arg);
  ****************************************************************************/
 
 #ifdef CONFIG_SMP
-int arm_pause_async_handler(int irq, void *context, void *arg);
+int arm_smp_sched_handler(int irq, void *context, void *arg);
 #endif
 
 /****************************************************************************