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Digital design fundamentals

Copyright notice

The notes below are modified copies of the academic module CS-120 “Digital Design”: http://www.csd.uoc.gr/~hy120/ copies or posting are not made or distributed for profit or commercial advantage.

© University of Crete.

http://www.csd.uoc.gr/~hy120/16f/copyright.html

• 1. Basic logic components
  • 1.1. SPDT switches
    • 1.1.1. Odd parity
    • 1.1.2. Even parity
  • 1.2 Relays
  • 1.3. Truth tables of logic gates
    • 1.3.1. NOT
    • 1.3.2. AND
    • 1.3.3. OR
    • 1.3.4. XOR
    • 1.3.5. NOR
    • 1.3.6. XNOR
• 2. Combinational circuits
  • 2.1. Decoder 2to4
  • 2.2. Multiplexer 4to1
  • 2.3. Encoding
    • 2.3.1. Seven segment display
  • 2.4. Adders
• 3. 2s complement
• 4. Memory components
  • 4.1. RS Flip-Flop with relays
  • 4.2. Latch
  • 4.3. Register
    • 4.3.1. Shift register
    • 4.3.2. Master-slave register
• 5. Sequential circuits
  • 5.1. Counter
  • 5.2. Finite state machine (FSM)
  • 5.3. Arithmetic logic unit (ALU)

Basic logic components

SPDT switches

Switches which have 3 pins (1 input, 2 output).

Odd Parity

Odd parity is the exclusive OR (XOR).

Even Parity

Even parity is the equality check.

Relays

Switches which can be used as memory. The relay below has a DPDT switch (double SPDT) and a coil. If the coil is activated (pins: 1, 8) the DPDT switch moves from its default state (input pins: 3, 6 to output pins: 2, 7) to the active state (input pins: 3, 6 to output pins: 4, 5). Relay have been used as basic memory components or mechanical clocks.

Relay 2-to-4

Truth tables of logic gates

In principle we need three basic gates to compose every other gate: logical NOT, logical AND, logical OR.

NOT

INPUT	OUTPUT
A	NOT A
0	1
1	0

CC BY-SA 3.0, Link

AND

INPUT	INPUT	OUTPUT
A	B	A AND B
0	0	0
0	1	0
1	0	0
1	1	1

By Inductiveload - Own work, Public Domain, Link

OR

INPUT	INPUT	OUTPUT
A	B	A OR B
0	0	0
0	1	1
1	0	1
1	1	1

By Inductiveload - Own work, Public Domain, Link

XOR

INPUT	INPUT	OUTPUT
A	B	A XOR B
0	0	0
0	1	1
1	0	1
1	1	0

By jjbeard - Own Drawing, made in Inkscape 0.43, Public Domain, Link

NOR

INPUT	INPUT	OUTPUT
A	B	A NOR B
0	0	1
0	1	0
1	0	0
1	1	0

By Inductiveload - Own work, Public Domain, Link

XNOR

XNOR is the logical equality.

INPUT	INPUT	OUTPUT
A	B	A NOR B
0	0	1
0	1	0
1	0	0
1	1	1

CC BY-SA 3.0, Link

Combinational circuits

High level description of combinational circuits.

Decoder 2to4

logisim file

./src/logisim/decoder_2_to_4.circ

Multiplexer 4to1

Multiplexer 4-to-1 using a decoder 2-to-4.

logisim file

./src/logisim/multiplexer_4_to_1.circ

A multiplexer’s module below.

By en:User:Cburnett - Own work This vector image was created with Inkscape., CC BY-SA 3.0, Link

Encoding

Seven segment display

By user:h2g2bob - Own work using Inkscape, CC BY-SA 3.0, Link

Combinational circuit and truth table

How to print numbers 0-3 to 7-segment alphanumeric display.

• You need only 2 bits to display numbers 0-3 using binary numbers
• Check which LEDs should be switched on (value = 1, ie. logical TRUE) to display number 0
  • Repeat for all numbers

In0	In1	-	A	B	C	D	E	F	G
0	0		1	1	1	1	1	1	0
0	1		0	1	1	0	0	0	0
1	0		1	1	0	1	1	0	1
1	1		1	1	1	1	0	0	1

How to make the logical functions

Express using basic logic operations (AND, NOT, OR) the output (7-segments) based on the input (2-bits)

A = NOT( In0’ ⋅ In1 )

B = 1

C = NOT( In0 ⋅ In1’ )

D = A

E = In1’

F = In0’ ⋅ In1’

G = In0

Adders

Half-adder and full-adder implementation.

logisim file

./src/logisim/half_full_adder.circ

2s complement

The inner circle shows the unsigned numbers (1s complement), the outer (helix) shows the signed numbers (2s complement).

Memory components

RS Flip-Flop with relays

Makes use positive feedback to create a latch, 1 bit of mechanical memory.

Latch

Latches are basic module for implementing memory.

logisim file

./src/logisim/latches_RS_D.circ

Register

Shift register

logisim file

./src/logisim/shift_register.circ

Master-slave register

The basic memory component. Below master-slave register using two latches RS, activated by positive edge clock.

logisim file

./src/logisim/master_slave_register.circ

Sequential circuits

High level description of sequential circuits.

Counter

A 3 bit counter.

logisim file

./src/logisim/3_bit_counter.circ

Finite state machine (FSM)

FSM for adaptive control of traffic lights. A and B are cars on a crossroad.

logisim file

./src/logisim/analogy_1_to_1.circ

S	Ad	Bd			Ago	Bgo	nS
0	0	0			0	0	0
0	0	1			0	1	1
0	1	0			1	0	0
0	1	1			0	1	1
1	0	0			0	0	1
1	0	1			0	1	1
1	1	0			1	0	0
1	1	1			1	0	0

• Ago = Ad · [ S + (S’)·(Bd’) ]
• Bgo = Bd · [ S’ + (S)·(Ad’) ]
• nS = S · Ad’ + S’ · Bd

Arithmetic Logic Unit (ALU)

A basic component which can do multiple functions, like addition, subtraction, logical AND etc.

logisim file

./src/logisim/ALU.circ

mode:
000	ALUout		A+B	(add)
001	ALUout		A-B	(sub)
010	ALUout		A AND B	(and)
011	ALUout		NOT (A OR B)	(nor)
1xx	ALUout		B	(passB)