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multiplexer_4_to_1.circ
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="2.13.20" version="1.0">
This file is intended to be loaded by Logisim-evolution (https://github.com/reds-heig/logisim-evolution).
<lib desc="#Wiring" name="0"/>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2">
<tool name="Multiplexer">
<a name="enable" val="false"/>
</tool>
<tool name="Demultiplexer">
<a name="enable" val="false"/>
</tool>
</lib>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4">
<tool name="ROM">
<a name="contents">addr/data: 8 8
0
</a>
</tool>
</lib>
<lib desc="#I/O" name="5"/>
<lib desc="#HDL-IP" name="6">
<tool name="VHDL Entity">
<a name="content">--------------------------------------------------------------------------------
-- HEIG-VD, institute REDS, 1400 Yverdon-les-Bains
-- Project :
-- File :
-- Autor :
-- Date :
--
--------------------------------------------------------------------------------
-- Description :
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
entity VHDL_Component is
port(
------------------------------------------------------------------------------
--Insert input ports below
horloge_i : in std_logic; -- input bit example
val_i : in std_logic_vector(3 downto 0); -- input vector example
------------------------------------------------------------------------------
--Insert output ports below
max_o : out std_logic; -- output bit example
cpt_o : out std_logic_Vector(3 downto 0) -- output vector example
);
end VHDL_Component;
--------------------------------------------------------------------------------
--Complete your VHDL description below
architecture type_architecture of VHDL_Component is
begin
end type_architecture;
</a>
</tool>
</lib>
<lib desc="#TCL" name="7">
<tool name="TclGeneric">
<a name="content">library ieee;
use ieee.std_logic_1164.all;
entity TCL_Generic is
port(
--Insert input ports below
horloge_i : in std_logic; -- input bit example
val_i : in std_logic_vector(3 downto 0); -- input vector example
--Insert output ports below
max_o : out std_logic; -- output bit example
cpt_o : out std_logic_Vector(3 downto 0) -- output vector example
);
end TCL_Generic;
</a>
</tool>
</lib>
<lib desc="#Base" name="8">
<tool name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
</lib>
<lib desc="#BFH-Praktika" name="9"/>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
<a name="tickmain" val="half_period"/>
</options>
<mappings>
<tool lib="8" map="Button2" name="Menu Tool"/>
<tool lib="8" map="Button3" name="Menu Tool"/>
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="8" name="Poke Tool"/>
<tool lib="8" name="Edit Tool"/>
<tool lib="8" name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
<a name="labelloc" val="east"/>
</tool>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
</toolbar>
<circuit name="main">
<a name="circuit" val="main"/>
<a name="clabel" val=""/>
<a name="clabelup" val="east"/>
<a name="clabelfont" val="SansSerif bold 16"/>
<a name="circuitnamedbox" val="true"/>
<a name="circuitvhdlpath" val=""/>
<wire from="(390,340)" to="(450,340)"/>
<wire from="(260,180)" to="(260,340)"/>
<wire from="(210,200)" to="(340,200)"/>
<wire from="(290,100)" to="(340,100)"/>
<wire from="(260,480)" to="(290,480)"/>
<wire from="(260,340)" to="(340,340)"/>
<wire from="(180,480)" to="(180,500)"/>
<wire from="(180,280)" to="(180,360)"/>
<wire from="(210,120)" to="(210,200)"/>
<wire from="(290,100)" to="(290,260)"/>
<wire from="(110,240)" to="(340,240)"/>
<wire from="(430,180)" to="(430,210)"/>
<wire from="(430,210)" to="(480,210)"/>
<wire from="(260,180)" to="(340,180)"/>
<wire from="(390,180)" to="(430,180)"/>
<wire from="(290,470)" to="(290,480)"/>
<wire from="(110,160)" to="(340,160)"/>
<wire from="(450,200)" to="(480,200)"/>
<wire from="(260,340)" to="(260,480)"/>
<wire from="(530,220)" to="(590,220)"/>
<wire from="(210,120)" to="(340,120)"/>
<wire from="(390,100)" to="(450,100)"/>
<wire from="(180,360)" to="(340,360)"/>
<wire from="(210,470)" to="(210,480)"/>
<wire from="(110,80)" to="(340,80)"/>
<wire from="(180,280)" to="(340,280)"/>
<wire from="(390,260)" to="(430,260)"/>
<wire from="(180,480)" to="(210,480)"/>
<wire from="(290,260)" to="(340,260)"/>
<wire from="(450,240)" to="(450,340)"/>
<wire from="(210,200)" to="(210,440)"/>
<wire from="(180,360)" to="(180,480)"/>
<wire from="(110,320)" to="(340,320)"/>
<wire from="(430,230)" to="(480,230)"/>
<wire from="(260,480)" to="(260,500)"/>
<wire from="(450,100)" to="(450,200)"/>
<wire from="(290,260)" to="(290,440)"/>
<wire from="(430,230)" to="(430,260)"/>
<wire from="(450,240)" to="(480,240)"/>
<comp lib="1" loc="(390,180)" name="AND Gate">
<a name="inputs" val="3"/>
</comp>
<comp lib="1" loc="(210,440)" name="NOT Gate">
<a name="facing" val="north"/>
</comp>
<comp lib="0" loc="(260,500)" name="Pin">
<a name="facing" val="north"/>
</comp>
<comp lib="0" loc="(590,220)" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
</comp>
<comp lib="1" loc="(390,260)" name="AND Gate">
<a name="inputs" val="3"/>
</comp>
<comp lib="0" loc="(110,80)" name="Pin"/>
<comp lib="1" loc="(530,220)" name="OR Gate">
<a name="inputs" val="4"/>
</comp>
<comp lib="1" loc="(390,100)" name="AND Gate">
<a name="inputs" val="3"/>
</comp>
<comp lib="1" loc="(290,440)" name="NOT Gate">
<a name="facing" val="north"/>
</comp>
<comp lib="0" loc="(180,500)" name="Pin">
<a name="facing" val="north"/>
</comp>
<comp lib="1" loc="(390,340)" name="AND Gate">
<a name="inputs" val="3"/>
</comp>
<comp lib="0" loc="(110,240)" name="Pin"/>
<comp lib="0" loc="(110,320)" name="Pin"/>
<comp lib="0" loc="(110,160)" name="Pin"/>
</circuit>
</project>