November_Tasking

Tasking - Possibly for November 2020 shuttle on Google-Skywater process

Plan a design from start to finish
Develop design in Verilog
Prototype Verilog design on FPGA (more than one vendor)
- Simulate, verify, operate on hardware, repeat
Integrate design with OpenLANE and target Google+Skywater PDK
Simulate post-implementation
Ship

From FPGA-ASIC. notes:

Look at synthesis-implementation reports
- Stay away from vendor-specific IP
  - 1st party vendor tools like to infer certain hard-silicon blocks based on what you are doing which may be deceiving if you just want to observe register/LUT use. These hard-silicon blocks may be quite large yet are being used for something small
Try to make design as portable as possible across different FPGA platforms
- Going back to previous statement, this means:
  - No PLL, analog, memory blocks, clocking IP, SERDES, any hard-IP, only LUT+register
Verification - simulation is important.
- Multiple phases of simulation: Behavioral, synthesis/implementation based
  - Behavioral will only get us just that - verification of the behavior of the design to ensure logic statements are operating as intended.
  - Post-implementation provides simulation model on the timing characteristics of what is going on inside the FPGA - this way somewhat realistic timing characteristics can be observed. This will vary significantly based on the target device and tooling used to generate these models - can setup scenarios for "worst-case". Currently unsure how models work for results of OpenLANE, etc..
- Pipeline to get the best timing - everything is a game of "red-light; green-light". This is typical in FPGA designs as registers are "free" (typically follow the output directly of a mux'd lookup table).
Use current PDK process - no internal clocking - just rely on external clock

Tri-State inputs? How do we make an pin that is either input, output, etc and switch in software
Power On Reset - how do we get the processor to boot up into a known state for some registers (like at least the program counter)?
Voltage shock protection on pins
Packaging and wire bonding planning
design rule checking and verification at every step of the process... to ensure the final mask is free of bugs.
Mixing clock domains - can be tricky based on metastability, timing comes into play heavily here - come up with multi-register hand-shake, synchronizer, FIFO, etc.. design
- do we need to do something special on input pins here?
Figure out how much current we can safely source/sink on output pins