Add support for exclusive L1

* Add an option to model non-inclusive LLC (l1). When turned on,
demand req will be steered into MLC directly, and L1 works as
victim cache to MLC.

* Bug fix in mlc_fill

* Fix the lost of dirty bit when promoting L1 line to MLC. Use the
dirty_l0 from req to carry the dirtyness info

* Revised the mlc_hit logic. Req hit in mlc should be sent to
cores' fill queues instead of directly calling done_func at MLC

* Fix the code format

src/globals/utils.h

@@ -282,6 +282,9 @@
 #define MIN4(v0, v1, v2, v3) (MIN2(MIN2((v0), (v1)), MIN2((v2), (v3))))
 #define MAX4(v0, v1, v2, v3) (MAX2(MAX2((v0), (v1)), MAX2((v2), (v3))))
 
+// a is the original addr, num is the shift amt before interleaving (usually
+// the cacheline), int is the interleave factor. The bank idx computed here
+// is simply the lower bits
 #define BANK(a, num, int) ((a) >> LOG2(int) & N_BIT_MASK(LOG2(num)))
 #define CHANNEL(bank, num) ((bank) >> LOG2(num))
 #define BANK_IN_CHANNEL(bank, num) ((bank)&N_BIT_MASK(LOG2(num)))

src/libs/cache_lib.c

@@ -70,12 +70,13 @@ char rand_repl_state[31];
 
 /**************************************************************************************/
 /**
- * @brief Return set index of the addr 
- * As a side-effect, the tag and line_addr will be populated 
- * @param cache 
+ * @brief Return set index of the addr
+ * As a side-effect, the tag and line_addr will be populated
+ * @param cache
  * @param addr The access addr (input)
  * @param tag  The tag of the access (output)
- * @param line_addr The base address of the cache blk corresponding to the access (output)
+ * @param line_addr The base address of the cache blk corresponding to the
+ * access (output)
  * @return uns The set index of the access
  */
 static inline uns cache_index(Cache* cache, Addr addr, Addr* tag,
@@ -207,11 +208,11 @@ void init_cache(Cache* cache, const char* name, uns cache_size, uns assoc,
 
 /**
  * @brief access the address.
- * 
- * @param cache 
- * @param addr the request addr 
- * @param line_addr 
- * @param update_repl 
+ *
+ * @param cache
+ * @param addr the request addr
+ * @param line_addr
+ * @param update_repl
  * @return void* data field of the blk or NULL if cache miss
  */
 void* cache_access(Cache* cache, Addr addr, Addr* line_addr, Flag update_repl) {
@@ -223,7 +224,7 @@ void* cache_access(Cache* cache, Addr addr, Addr* line_addr, Flag update_repl) {
     return access_ideal_storage(cache, set, tag, addr);
   }
 
-  //search the ways
+  // search the ways
   for(ii = 0; ii < cache->assoc; ii++) {
     Cache_Entry* line = &cache->entries[set][ii];
 
@@ -266,22 +267,22 @@ void* cache_access(Cache* cache, Addr addr, Addr* line_addr, Flag update_repl) {
 
 /**
  * @brief Insert new addr to the cache
- * 
+ *
  * This function is a wrapper of cache_insert_replpos, see below
- * 
- * Note cache_insert is intrusive, for a non-instusive function 
- * (which only pick out the victim but not doing the insertion), 
+ *
+ * Note cache_insert is intrusive, for a non-instusive function
+ * (which only pick out the victim but not doing the insertion),
  * see get_next_repl_line, both of these functions calls find_repl_entry
  * internally
- * 
+ *
  * DON'T call this unless you are sure that the line is not in the
  * cache (call after cache_access returned NULL)
- * 
- * @param cache 
- * @param proc_id 
- * @param addr 
- * @param line_addr 
- * @param repl_line_addr 
+ *
+ * @param cache
+ * @param proc_id
+ * @param addr
+ * @param line_addr
+ * @param repl_line_addr
  * @return void* The data field of the inserted blk
  */
 void* cache_insert(Cache* cache, uns8 proc_id, Addr addr, Addr* line_addr,
@@ -295,16 +296,16 @@ void* cache_insert(Cache* cache, uns8 proc_id, Addr addr, Addr* line_addr,
  *  returns a pointer to the data section of the new cache line.
  *  Sets line_addr to the address of the first block of the new line.  Sets
  *  repl_line_addr to the address of the first block that was replaced
- * 
+ *
  *  Note this func won't do the WB if the victim is dirty, the info of the
  *  victim blk is returned and WB is handled by the caller of this func
- * 
+ *
  *  DON'T call this unless you are sure that the line is *not* in the
  *  cache (call after cache_access returned NULL)
- * @param cache 
- * @param proc_id 
+ * @param cache
+ * @param proc_id
  * @param addr The addr of the blk to be inserted
- * @param line_addr The base addr of the blk to be insert (input) 
+ * @param line_addr The base addr of the blk to be insert (input)
  * @param repl_line_addr The base addr of the blk got evicted (output)
  * @return void* The data field of the inserted blk
  */
@@ -321,13 +322,13 @@ void* cache_insert_replpos(Cache* cache, uns8 proc_id, Addr addr,
     new_line        = insert_sure_line(cache, set, tag);
     *repl_line_addr = 0;
   } else {
-    //new_line points to the victim, repl_index is the way id for the victim
+    // new_line points to the victim, repl_index is the way id for the victim
     new_line = find_repl_entry(cache, proc_id, set, &repl_index);
     /* before insert the data into cache, if the cache has shadow entry */
     /* insert that entry to the shadow cache */
     if((cache->repl_policy == REPL_SHADOW_IDEAL) && new_line->valid)
       shadow_cache_insert(cache, set, new_line->tag, new_line->base);
-    if(new_line->valid){
+    if(new_line->valid) {
       // bug fixed. 4/26/04 if the entry is not valid,
       // repl_line_addr should be set to 0
       *repl_line_addr = new_line->base;
@@ -443,13 +444,13 @@ void* cache_insert_replpos(Cache* cache, uns8 proc_id, Addr addr,
 
 
 /**
- * @brief Invalid the blk by address if presented, no wb even the blk 
+ * @brief Invalidate the blk by address if presented, no wb even the blk
  * is dirty
- * 
- * @param cache 
- * @param addr 
- * @param line_addr 
- * @param True on find in cache, False on no present 
+ *
+ * @param cache
+ * @param addr
+ * @param line_addr
+ * @param True on find in cache, False on no present
  */
 void cache_invalidate(Cache* cache, Addr addr, Addr* line_addr) {
   Addr tag;
@@ -472,9 +473,9 @@ void cache_invalidate(Cache* cache, Addr addr, Addr* line_addr) {
 
 /**
  * @brief Return a pointer to the victim to be replaced
- * 
+ *
  * The caller of this func is supposed to handle the possible
- * writeback correctly, otherwise the correctness of simulation 
+ * writeback correctly, otherwise the correctness of simulation
  * is compromised
  *
  * @param cache

src/memory/mem_req.h

@@ -131,7 +131,15 @@ struct Mem_Req_struct {
   uns  op_count;  /* number of ops that are waiting for the miss */
   uns  req_count; /* number of requests coalesced into this one */
   Flag (*done_func)(struct Mem_Req_struct*); /* pointer to function to call when
-                                                the memory request is finished
+                                                the memory request is finished,
+                                                this is the mechanism scarab
+                                                used to implement a "callback".
+                                                i.e. when a req is finally
+                                                returned from the mem system,
+                                                continue with the rest of the
+                                                process. This is mostly used by
+                                                I$ and D$ to fill the line when
+                                                req returned from uncore/mem
                                               */
   Flag mlc_miss;                             /* did this request miss in MLC */
   Flag mlc_miss_satisfied;   /* did this request miss in MLC and it is already