Fixup for ddac7f5: Added usize arithmetics for riscv64::VirtAddr

src/arch/riscv64.rs

@@ -134,6 +134,41 @@ impl From<usize> for VirtAddr {
     }
 }
 
+#[cfg(target_pointer_width = "64")]
+// if the target_pointer_width is 64, usize = u64 so we can safely add
+impl core::ops::Add<usize> for VirtAddr {
+    type Output = Self;
+    #[inline]
+    fn add(self, rhs: usize) -> Self::Output {
+        VirtAddr::new(self.0 + rhs as u64)
+    }
+}
+#[cfg(target_pointer_width = "64")]
+// if the target_pointer_width is 64, usize = u64 so we can safely add
+impl core::ops::AddAssign<usize> for VirtAddr {
+    #[inline]
+    fn add_assign(&mut self, rhs: usize) {
+        *self = *self + rhs;
+    }
+}
+#[cfg(target_pointer_width = "64")]
+// if the target_pointer_width is 64, usize = u64 so we can safely sub
+impl core::ops::Sub<usize> for VirtAddr {
+    type Output = Self;
+    #[inline]
+    fn sub(self, rhs: usize) -> Self::Output {
+        VirtAddr::new(self.0.checked_sub(rhs as u64).unwrap())
+    }
+}
+#[cfg(target_pointer_width = "64")]
+// if the target_pointer_width is 64, usize = u64 so we can safely sub
+impl core::ops::SubAssign<usize> for VirtAddr {
+    #[inline]
+    fn sub_assign(&mut self, rhs: usize) {
+        *self = *self - rhs;
+    }
+}
+
 #[cfg(target_pointer_width = "64")]
 // if the target_pointer_width is 64, usize = u64 so we can safely transform.
 impl From<usize> for PhysAddr {