Reduce clock slightly for better hirez VGA compatibility

harbaum · Feb 26, 2024 · 543466a · 543466a
1 parent f61df46
commit 543466a
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Showing 3 changed files with 8 additions and 8 deletions.
diff --git a/OLD_VERSIONS.md b/OLD_VERSIONS.md
@@ -2,8 +2,8 @@
 
 ## IRQ in version 1.2.2
 
-Since version 1.2.2 MiSTeryNano the [M0S/BL616
-MCU](https://github.com/harbaum/MiSTeryNano/tree/main/bl616)
+Since version 1.2.2 MiSTeryNano the [firmware for the M0S/BL616
+MCU](firmware/misterynano_fw)
 has an additional IRQ connection to the FPGA for faster
 response times.
 

diff --git a/src/tang/mega138k/gowin_pll/pll_160m.v b/src/tang/mega138k/gowin_pll/pll_160m.v
@@ -5,7 +5,7 @@
 //Part Number: GW5AST-LV138FPG676AES
 //Device: GW5AST-138B
 //Device Version: B
-//Created Time: Fri Feb 16 17:07:03 2024
+//Created Time: Mon Feb 26 08:15:45 2024
 
 module pll_160m (lock, clkout, clkin);
 
@@ -80,14 +80,14 @@ PLL PLL_inst (
 defparam PLL_inst.FCLKIN = "50";
 defparam PLL_inst.IDIV_SEL = 1;
 defparam PLL_inst.FBDIV_SEL = 1;
-defparam PLL_inst.ODIV0_SEL = 5;
+defparam PLL_inst.ODIV0_SEL = 6;
 defparam PLL_inst.ODIV1_SEL = 8;
 defparam PLL_inst.ODIV2_SEL = 8;
 defparam PLL_inst.ODIV3_SEL = 8;
 defparam PLL_inst.ODIV4_SEL = 8;
 defparam PLL_inst.ODIV5_SEL = 8;
 defparam PLL_inst.ODIV6_SEL = 8;
-defparam PLL_inst.MDIV_SEL = 16;
+defparam PLL_inst.MDIV_SEL = 19;
 defparam PLL_inst.MDIV_FRAC_SEL = 0;
 defparam PLL_inst.ODIV0_FRAC_SEL = 0;
 defparam PLL_inst.CLKOUT0_EN = "TRUE";

diff --git a/src/tang/primer25k/gowin_pll/pll_160m.v b/src/tang/primer25k/gowin_pll/pll_160m.v
@@ -5,7 +5,7 @@
 //Part Number: GW5A-LV25MG121NC1/I0
 //Device: GW5A-25
 //Device Version: A
-//Created Time: Thu Feb 15 13:22:30 2024
+//Created Time: Mon Feb 26 08:06:13 2024
 
 module pll_160m (lock, clkout, clkin);
 
@@ -58,14 +58,14 @@ PLLA PLLA_inst (
 defparam PLLA_inst.FCLKIN = "50";
 defparam PLLA_inst.IDIV_SEL = 1;
 defparam PLLA_inst.FBDIV_SEL = 1;
-defparam PLLA_inst.ODIV0_SEL = 5;
+defparam PLLA_inst.ODIV0_SEL = 6;
 defparam PLLA_inst.ODIV1_SEL = 8;
 defparam PLLA_inst.ODIV2_SEL = 8;
 defparam PLLA_inst.ODIV3_SEL = 8;
 defparam PLLA_inst.ODIV4_SEL = 8;
 defparam PLLA_inst.ODIV5_SEL = 8;
 defparam PLLA_inst.ODIV6_SEL = 8;
-defparam PLLA_inst.MDIV_SEL = 16;
+defparam PLLA_inst.MDIV_SEL = 19;
 defparam PLLA_inst.MDIV_FRAC_SEL = 0;
 defparam PLLA_inst.ODIV0_FRAC_SEL = 0;
 defparam PLLA_inst.CLKOUT0_EN = "TRUE";