zinc: refactor cfg test -> target_arch and target_os where possible

src/hal/cortex_common/irq.rs

@@ -50,18 +50,18 @@ static mut irq_level : usize = 0;
 /// Note that this is reference counted: if `disable_irqs` is called
 /// twice then interrupts will only be re-enabled upon the second call
 /// to `enable_irqs`.
-#[cfg(not(test))]
+#[cfg(target_os = "none")]
 #[inline(always)]
 unsafe fn disable_irqs() {
   asm!("cpsid i" :::: "volatile");
   irq_level += 1;
 }
 
-#[cfg(test)]
+#[cfg(not(target_os = "none"))]
 unsafe fn disable_irqs() { unimplemented!() }
 
 /// Enables all interrupts except Reset, HardFault, and NMI.
-#[cfg(not(test))]
+#[cfg(target_os = "none")]
 #[inline(always)]
 unsafe fn enable_irqs() {
   if irq_level == 0 {
@@ -75,5 +75,5 @@ unsafe fn enable_irqs() {
   }
 }
 
-#[cfg(test)]
+#[cfg(not(target_os = "none"))]
 unsafe fn enable_irqs() { unimplemented!() }

src/hal/isr.rs

@@ -21,7 +21,6 @@
 #[cfg(feature = "cpu_cortex-m3")]
 #[path="cortex_m3/isr.rs"] pub mod isr_cortex_m3;
 
-// TODO(mcoffin): create cortex-m4 isr module
 #[cfg(feature = "cpu_cortex-m4")]
 #[path="cortex_m3/isr.rs"] pub mod isr_cortex_m4;
 

src/hal/mod.rs

@@ -48,5 +48,5 @@ pub mod stack;
 pub mod timer;
 pub mod uart;
 
-#[cfg(not(test))]
+#[cfg(target_os = "none")]
 pub mod isr;

src/util/shared.rs

@@ -34,7 +34,7 @@ mod dummy_irq {
 
   impl NoInterrupts {
     pub fn new() -> NoInterrupts {
-      NoInterrupts;
+      NoInterrupts
     }
   }
 }

src/util/support.rs

@@ -15,25 +15,15 @@
 
 //! Support functions currently required by the linker for bare-metal targets.
 
-#[doc(hidden)]
-#[cfg(test)]
-#[no_stack_check]
-#[no_mangle]
-pub extern fn breakpoint() { unimplemented!() }
-
-/// Call the debugger.
-#[cfg(all(not(test), target_arch = "arm"))]
-#[no_stack_check]
-#[no_mangle]
-pub extern fn breakpoint() {
-  unsafe { asm!("bkpt") }
-}
+pub use core::intrinsics::breakpoint;
 
 /// Call the debugger and halts execution.
 #[no_stack_check]
 #[no_mangle]
 pub extern fn abort() -> ! {
-  breakpoint();
+  unsafe {
+    breakpoint();
+  }
   loop {}
 }
 
@@ -49,26 +39,26 @@ pub extern fn __aeabi_memset(dest: *mut u8, size: usize, value: u32) {
   }
 }
 
-#[cfg(all(not(test), target_arch = "arm"))]
+#[cfg(target_arch = "arm")]
 #[inline(always)]
 /// NOP instruction
 pub fn nop() {
   unsafe { asm!("nop" :::: "volatile"); }
 }
 
-#[cfg(test)]
+#[cfg(not(target_arch = "arm"))]
 /// NOP instruction (mock)
 pub fn nop() {
 }
 
-#[cfg(all(not(test), target_arch = "arm"))]
+#[cfg(target_arch = "arm")]
 #[inline(always)]
 /// WFI instruction
 pub fn wfi() {
     unsafe { asm!("wfi" :::: "volatile"); }
 }
 
-#[cfg(test)]
+#[cfg(not(target_arch = "arm"))]
 /// WFI instruction (mock)
 pub fn wfi() {
 }