rename stuff

griffi-gh · Oct 9, 2023 · be74e9d · be74e9d
1 parent 4ab081e
commit be74e9d
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Showing 2 changed files with 10 additions and 10 deletions.
diff --git a/yarge-core/src/bus.rs b/yarge-core/src/bus.rs
@@ -67,10 +67,10 @@ impl MemBus {
         0xFF00 => self.input.get_joyp(),
         0xFF01 => self.serial.read_sb(),
         0xFF02 => self.serial.read_sc(),
-        0xFF04 => self.timers.get_div(),
-        0xFF05 => self.timers.get_tima(),
+        0xFF04 => self.timers.read_div(),
+        0xFF05 => self.timers.read_tima(),
         0xFF06 => self.timers.tma,
-        0xFF07 => self.timers.get_tac(),
+        0xFF07 => self.timers.read_tac(),
         0xFF0F => self.iif,
         //0xFF10..=0xFF26 => self.tmp_apu_reg[addr as usize - 0xFF10],
         0xFF10..=0xFF3F => self.apu.read(addr),
@@ -123,9 +123,9 @@ impl MemBus {
         0xFF01 => { self.serial.write_sb(value) },
         0xFF02 => { self.serial.write_sc(value) },
         0xFF04 => { self.timers.reset_div() },
-        0xFF05 => { self.timers.set_tima(value) },
+        0xFF05 => { self.timers.write_tima_tick(value, &mut self.iif) },
         0xFF06 => { self.timers.tma = value },
-        0xFF07 => { self.timers.set_tac(value) },
+        0xFF07 => { self.timers.write_tac(value) },
         0xFF0F => { self.iif = value },
         // 0xFF10..=0xFF26 => { self.tmp_apu_reg[addr as usize - 0xFF10] = value; }
         0xFF10..=0xFF3F => { self.apu.write(addr, value, blocking) }

diff --git a/yarge-core/src/timers.rs b/yarge-core/src/timers.rs
@@ -28,25 +28,25 @@ impl Timers {
   pub fn get_div_raw(&self) -> u16 {
     self.div
   }
-  pub fn get_div(&self) -> u8 {
+  pub fn read_div(&self) -> u8 {
     (self.div >> 8) as u8
   }
   pub fn reset_div(&mut self) {
     self.div = 0;
   }
 
-  pub fn get_tima(&self) -> u8 {
+  pub fn read_tima(&self) -> u8 {
     self.tima
   }
-  pub fn set_tima(&mut self, value: u8) {
+  pub fn write_tima(&mut self, value: u8) {
     self.tima = value;
     self.tima_reset_pending = false;
   }
 
-  pub fn get_tac(&self) -> u8 {
+  pub fn read_tac(&self) -> u8 {
     ((self.enable as u8) << 2) | self.rate
   }
-  pub fn set_tac(&mut self, value: u8) {
+  pub fn write_tac(&mut self, value: u8) {
     self.enable = value & 0b100 != 0;
     self.rate = value & 0b11;
   }