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Add missing hlsl-fxc tests. All subgroup operations are unsupported before Shader Model 6.0 so they are skipped. Bug: 354738715 Change-Id: I6ceaf8c4358e5ad947a117fa0c2d278ceafdc6e4 Reviewed-on: https://dawn-review.googlesource.com/c/dawn/+/202695 Reviewed-by: Antonio Maiorano <[email protected]> Commit-Queue: Natalie Chouinard <[email protected]> Commit-Queue: Antonio Maiorano <[email protected]> Auto-Submit: Natalie Chouinard <[email protected]>
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/0464d1.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
vector<float16_t, 2> quadBroadcast_0464d1() { | ||
vector<float16_t, 2> res = QuadReadLaneAt((float16_t(1.0h)).xx, 1); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store<vector<float16_t, 2> >(0u, quadBroadcast_0464d1()); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store<vector<float16_t, 2> >(0u, quadBroadcast_0464d1()); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/0639ea.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
int quadBroadcast_0639ea() { | ||
int res = QuadReadLaneAt(1, 1u); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store(0u, asuint(quadBroadcast_0639ea())); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store(0u, asuint(quadBroadcast_0639ea())); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/0cc513.wgsl.expected.ir.fxc.hlsl
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@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
float3 quadBroadcast_0cc513() { | ||
float3 res = QuadReadLaneAt((1.0f).xxx, 1u); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store3(0u, asuint(quadBroadcast_0cc513())); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store3(0u, asuint(quadBroadcast_0cc513())); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/0e0e6e.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
int3 quadBroadcast_0e0e6e() { | ||
int3 res = QuadReadLaneAt((1).xxx, 1u); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store3(0u, asuint(quadBroadcast_0e0e6e())); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store3(0u, asuint(quadBroadcast_0e0e6e())); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/2d0b7d.wgsl.expected.ir.fxc.hlsl
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@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
uint4 quadBroadcast_2d0b7d() { | ||
uint4 res = QuadReadLaneAt((1u).xxxx, 1u); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store4(0u, quadBroadcast_2d0b7d()); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store4(0u, quadBroadcast_2d0b7d()); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/355db5.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
float3 quadBroadcast_355db5() { | ||
float3 res = QuadReadLaneAt((1.0f).xxx, 1); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store3(0u, asuint(quadBroadcast_355db5())); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store3(0u, asuint(quadBroadcast_355db5())); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/3c3824.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
vector<float16_t, 2> quadBroadcast_3c3824() { | ||
vector<float16_t, 2> res = QuadReadLaneAt((float16_t(1.0h)).xx, 1u); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store<vector<float16_t, 2> >(0u, quadBroadcast_3c3824()); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store<vector<float16_t, 2> >(0u, quadBroadcast_3c3824()); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/4d9898.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
vector<float16_t, 4> quadBroadcast_4d9898() { | ||
vector<float16_t, 4> res = QuadReadLaneAt((float16_t(1.0h)).xxxx, 1); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store<vector<float16_t, 4> >(0u, quadBroadcast_4d9898()); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store<vector<float16_t, 4> >(0u, quadBroadcast_4d9898()); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/641316.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
uint2 quadBroadcast_641316() { | ||
uint2 res = QuadReadLaneAt((1u).xx, 1); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store2(0u, quadBroadcast_641316()); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store2(0u, quadBroadcast_641316()); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/704803.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
int3 quadBroadcast_704803() { | ||
int3 res = QuadReadLaneAt((1).xxx, 1); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store3(0u, asuint(quadBroadcast_704803())); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store3(0u, asuint(quadBroadcast_704803())); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/76f499.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
int4 quadBroadcast_76f499() { | ||
int4 res = QuadReadLaneAt((1).xxxx, 1); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store4(0u, asuint(quadBroadcast_76f499())); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store4(0u, asuint(quadBroadcast_76f499())); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/78129b.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
float16_t quadBroadcast_78129b() { | ||
float16_t res = QuadReadLaneAt(float16_t(1.0h), 1); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store<float16_t>(0u, quadBroadcast_78129b()); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store<float16_t>(0u, quadBroadcast_78129b()); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/796753.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
vector<float16_t, 3> quadBroadcast_796753() { | ||
vector<float16_t, 3> res = QuadReadLaneAt((float16_t(1.0h)).xxx, 1); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store<vector<float16_t, 3> >(0u, quadBroadcast_796753()); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store<vector<float16_t, 3> >(0u, quadBroadcast_796753()); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/820991.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
float4 quadBroadcast_820991() { | ||
float4 res = QuadReadLaneAt((1.0f).xxxx, 1u); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store4(0u, asuint(quadBroadcast_820991())); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store4(0u, asuint(quadBroadcast_820991())); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/960c6b.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
float quadBroadcast_960c6b() { | ||
float res = QuadReadLaneAt(1.0f, 1u); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store(0u, asuint(quadBroadcast_960c6b())); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store(0u, asuint(quadBroadcast_960c6b())); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/9d802c.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
float4 quadBroadcast_9d802c() { | ||
float4 res = QuadReadLaneAt((1.0f).xxxx, 1); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store4(0u, asuint(quadBroadcast_9d802c())); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store4(0u, asuint(quadBroadcast_9d802c())); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/a2d2b4.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
uint quadBroadcast_a2d2b4() { | ||
uint res = QuadReadLaneAt(1u, 1); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store(0u, quadBroadcast_a2d2b4()); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store(0u, quadBroadcast_a2d2b4()); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/ae401e.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
uint3 quadBroadcast_ae401e() { | ||
uint3 res = QuadReadLaneAt((1u).xxx, 1u); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store3(0u, quadBroadcast_ae401e()); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store3(0u, quadBroadcast_ae401e()); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/b68331.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
uint4 quadBroadcast_b68331() { | ||
uint4 res = QuadReadLaneAt((1u).xxxx, 1); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store4(0u, quadBroadcast_b68331()); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store4(0u, quadBroadcast_b68331()); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/bed00b.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
int4 quadBroadcast_bed00b() { | ||
int4 res = QuadReadLaneAt((1).xxxx, 1u); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store4(0u, asuint(quadBroadcast_bed00b())); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store4(0u, asuint(quadBroadcast_bed00b())); | ||
} | ||
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18 changes: 18 additions & 0 deletions
18
test/tint/builtins/gen/literal/quadBroadcast/c0e704.wgsl.expected.ir.fxc.hlsl
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,18 @@ | ||
SKIP: Wave ops not supported before SM 6.0 | ||
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RWByteAddressBuffer prevent_dce : register(u0); | ||
int2 quadBroadcast_c0e704() { | ||
int2 res = QuadReadLaneAt((1).xx, 1); | ||
return res; | ||
} | ||
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void fragment_main() { | ||
prevent_dce.Store2(0u, asuint(quadBroadcast_c0e704())); | ||
} | ||
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[numthreads(1, 1, 1)] | ||
void compute_main() { | ||
prevent_dce.Store2(0u, asuint(quadBroadcast_c0e704())); | ||
} | ||
|
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