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Update LLVM (#1251)
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* reorder some test expectations
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alan-baker authored Oct 10, 2023
1 parent ce2b7f0 commit 1218538
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2 changes: 1 addition & 1 deletion deps.json
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
"subrepo" : "llvm/llvm-project",
"branch" : "main",
"subdir" : "third_party/llvm",
"commit" : "ceec9a7874af2eea8b00b5616fad388ccfa2b4f3"
"commit" : "9bcf9dc98a6829ae3b0b18aa82368def394af7f4"
},
{
"name" : "SPIRV-Headers",
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8 changes: 4 additions & 4 deletions test/HalfStorage/vstore_half3.cl
Original file line number Diff line number Diff line change
Expand Up @@ -34,16 +34,16 @@ __kernel void test(__global half *a, float3 b, int c) {
// CHECK: [[addr1:%[^ ]+]] = OpAccessChain %{{.*}} %{{.*}} [[uint0]] [[cx3]]
// CHECK: OpStore [[addr1]] [[val1i16]]

// CHECK-64: [[idx1:%[^ ]+]] = OpIAdd [[ulong]] [[cx3]] [[ulong1]]
// CHECK-32: [[idx1:%[^ ]+]] = OpIAdd [[uint]] [[cx3]] [[uint1]]
// CHECK: [[val2i32:%[^ ]+]] = OpExtInst [[uint]] {{.*}} PackHalf2x16
// CHECK: [[val2i16:%[^ ]+]] = OpUConvert [[ushort]] [[val2i32]]
// CHECK-64: [[idx1:%[^ ]+]] = OpIAdd [[ulong]] [[cx3]] [[ulong1]]
// CHECK-32: [[idx1:%[^ ]+]] = OpIAdd [[uint]] [[cx3]] [[uint1]]
// CHECK: [[addr2:%[^ ]+]] = OpAccessChain %{{.*}} %{{.*}} [[uint0]] [[idx1]]
// CHECK: OpStore [[addr2]] [[val2i16]]

// CHECK-64: [[idx2:%[^ ]+]] = OpIAdd [[ulong]] [[cx3]] [[ulong2]]
// CHECK-32: [[idx2:%[^ ]+]] = OpIAdd [[uint]] [[cx3]] [[uint2]]
// CHECK: [[val3i32:%[^ ]+]] = OpExtInst [[uint]] {{.*}} PackHalf2x16
// CHECK: [[val3i16:%[^ ]+]] = OpUConvert [[ushort]] [[val3i32]]
// CHECK-64: [[idx2:%[^ ]+]] = OpIAdd [[ulong]] [[cx3]] [[ulong2]]
// CHECK-32: [[idx2:%[^ ]+]] = OpIAdd [[uint]] [[cx3]] [[uint2]]
// CHECK: [[addr3:%[^ ]+]] = OpAccessChain %{{.*}} %{{.*}} [[uint0]] [[idx2]]
// CHECK: OpStore [[addr3]] [[val3i16]]

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