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Implement incremental tag collection and other major updates
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- `verilog-ext-tags-get` now collects and updates tags only for modified files
- Optimize tags collection algorithms
- Replace use of workspace with per project `verilog-ext-proj-alist`
- Optimize hierarchy processing functions
- Update async tags/hierarchy functions
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@gmlarumbe
gmlarumbe committed Oct 16, 2023
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2 changes: 1 addition & 1 deletion test-hdl
Submodule test-hdl updated 70 files
+4 −4 verilog/files/capf/verilog-ext/ref/tb_program.annotations.el
+8 −8 verilog/files/capf/verilog-ext/ref/tb_program.capf.el
+7 −7 verilog/files/capf/verilog-ext/ref/ucontroller.annotations.el
+10 −10 verilog/files/capf/verilog-ext/ref/ucontroller.capf.el
+2 −2 verilog/files/faceup/verilog-ts-mode/ref/axi_demux.faceup
+399 −399 verilog/files/faceup/verilog-ts-mode/ref/axi_test.faceup
+5 −5 verilog/files/faceup/verilog-ts-mode/ref/uvm_component.faceup
+17 −18 verilog/files/hierarchy/verilog-ext/ref/axi_demux.builtin.hier.el
+17 −18 verilog/files/hierarchy/verilog-ext/ref/axi_demux.builtin.outshine.sv
+18 −0 verilog/files/hierarchy/verilog-ext/ref/axi_demux.mm.builtin.hier.el
+26 −0 verilog/files/hierarchy/verilog-ext/ref/axi_demux.mm.builtin.outshine.sv
+18 −0 verilog/files/hierarchy/verilog-ext/ref/axi_demux.mm.ts.hier.el
+26 −0 verilog/files/hierarchy/verilog-ext/ref/axi_demux.mm.ts.outshine.sv
+17 −18 verilog/files/hierarchy/verilog-ext/ref/axi_demux.ts.hier.el
+17 −18 verilog/files/hierarchy/verilog-ext/ref/axi_demux.ts.outshine.sv
+4 −0 verilog/files/hierarchy/verilog-ext/ref/ucontroller.builtin.hier.el
+4 −0 verilog/files/hierarchy/verilog-ext/ref/ucontroller.builtin.outshine.sv
+4 −0 verilog/files/hierarchy/verilog-ext/ref/ucontroller.vhier.hier.el
+4 −4 verilog/files/hierarchy/verilog-ext/ref/ucontroller.vhier.outshine.sv
+245 −278 verilog/files/tags/verilog-ext/ref/axi_demux.defs.el
+2,255 −1,727 verilog/files/tags/verilog-ext/ref/axi_demux.refs.el
+303 −444 verilog/files/tags/verilog-ext/ref/axi_demux.ts.defs.el
+2,255 −1,708 verilog/files/tags/verilog-ext/ref/axi_demux.ts.refs.el
+1,173 −925 verilog/files/tags/verilog-ext/ref/axi_test.defs.el
+8,089 −5,122 verilog/files/tags/verilog-ext/ref/axi_test.refs.el
+1,213 −1,331 verilog/files/tags/verilog-ext/ref/axi_test.ts.defs.el
+8,047 −5,103 verilog/files/tags/verilog-ext/ref/axi_test.ts.refs.el
+6 −8 verilog/files/tags/verilog-ext/ref/instances.defs.el
+145 −192 verilog/files/tags/verilog-ext/ref/instances.refs.el
+2 −3 verilog/files/tags/verilog-ext/ref/instances.ts.defs.el
+145 −192 verilog/files/tags/verilog-ext/ref/instances.ts.refs.el
+38 −59 verilog/files/tags/verilog-ext/ref/tb_program.defs.el
+253 −211 verilog/files/tags/verilog-ext/ref/tb_program.refs.el
+36 −58 verilog/files/tags/verilog-ext/ref/tb_program.ts.defs.el
+253 −211 verilog/files/tags/verilog-ext/ref/tb_program.ts.refs.el
+90 −137 verilog/files/tags/verilog-ext/ref/ucontroller.defs.el
+369 −345 verilog/files/tags/verilog-ext/ref/ucontroller.refs.el
+92 −140 verilog/files/tags/verilog-ext/ref/ucontroller.ts.defs.el
+369 −345 verilog/files/tags/verilog-ext/ref/ucontroller.ts.refs.el
+226 −515 verilog/files/tags/verilog-ext/ref/uvm_component.defs.el
+3,943 −2,755 verilog/files/tags/verilog-ext/ref/uvm_component.refs.el
+1,147 −1,170 verilog/files/tags/verilog-ext/ref/uvm_component.ts.defs.el
+3,947 −2,753 verilog/files/tags/verilog-ext/ref/uvm_component.ts.refs.el
+86 −18 verilog/files/xref/verilog-ext/ref/ucontroller.xref.defs.el
+445 −99 verilog/files/xref/verilog-ext/ref/ucontroller.xref.refs.el
+293 −51 verilog/files/xref/verilog-ext/ref/uvm_component.xref.defs.el
+3,893 −724 verilog/files/xref/verilog-ext/ref/uvm_component.xref.refs.el
+13 −18 verilog/verilog-ext/test-hdl-verilog-ext-capf.el
+169 −84 verilog/verilog-ext/test-hdl-verilog-ext-hierarchy.el
+5 −3 verilog/verilog-ext/test-hdl-verilog-ext-navigation.el
+2 −4 verilog/verilog-ext/test-hdl-verilog-ext-setup-package.el
+1 −0 verilog/verilog-ext/test-hdl-verilog-ext-setup-straight.el
+101 −105 verilog/verilog-ext/test-hdl-verilog-ext-tags.el
+11 −18 verilog/verilog-ext/test-hdl-verilog-ext-xref.el
+2 −2 verilog/verilog-ext/test-hdl-verilog-ext.el
+396 −396 vhdl/files/faceup/vhdl-ts-mode/ref/axi_if_converter.faceup
+19 −19 vhdl/files/faceup/vhdl-ts-mode/ref/global_pkg.faceup
+18 −18 vhdl/files/faceup/vhdl-ts-mode/ref/global_sim.faceup
+10 −10 vhdl/files/faceup/vhdl-ts-mode/ref/indent_misc.faceup
+27 −27 vhdl/files/faceup/vhdl-ts-mode/ref/instances.faceup
+9 −9 vhdl/files/faceup/vhdl-ts-mode/ref/misc.faceup
+24 −24 vhdl/files/faceup/vhdl-ts-mode/ref/sexp.faceup
+327 −327 vhdl/files/faceup/vhdl-ts-mode/ref/std_logic_1164-body.faceup
+10 −10 vhdl/files/faceup/vhdl-ts-mode/ref/std_logic_1164.faceup
+307 −307 vhdl/files/faceup/vhdl-ts-mode/ref/tb_axi_if_converter.faceup
+2 −2 vhdl/files/xref/vhdl-ext/ref/axi_if_converter.xref.defs.el
+147 −147 vhdl/files/xref/vhdl-ext/ref/axi_if_converter.xref.refs.el
+1 −1 vhdl/files/xref/vhdl-ext/ref/global_sim.xref.defs.el
+1 −1 vhdl/files/xref/vhdl-ext/ref/global_sim.xref.refs.el
+11 −7 vhdl/vhdl-ext/test-hdl-vhdl-ext-tags.el
39 changes: 28 additions & 11 deletions verilog-ext-capf.el
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@

;;; Code:

(require 'verilog-ext-utils)
(require 'verilog-ext-tags)

;; Fetched from IEEE 1800-2012
;; https://ece.uah.edu/~gaede/cpe526/2012%20System%20Verilog%20Language%20Reference%20Manual.pdf
Expand Down Expand Up @@ -278,14 +278,20 @@ Return value is a cons with (start . end) bounds."
(when (and start end)
(cons start end))))

(defun verilog-ext-capf-annotation-function (cand defs-table inst-table)
(defun verilog-ext-capf-annotation-function (cand)
"Completion annotation function for candidate CAND.
Get candidate type from DEFS-TABLE, or if not found, from INST-TABLE."
(let* ((entry (or (and defs-table (gethash cand defs-table))
Get candidate type from `verilog-ext-tags-defs-table' or if not found, from
`verilog-ext-tags-inst-table'.
See available types in `verilog-ext-tags-definitions-ts-re'."
(let* ((proj (verilog-ext-buffer-proj))
(defs-table (alist-get proj verilog-ext-tags-defs-table nil nil #'string=))
(inst-table (alist-get proj verilog-ext-tags-inst-table nil nil #'string=))
(entry (or (and defs-table (gethash cand defs-table))
(and inst-table (gethash cand inst-table))))
(locs (plist-get entry :locs))
(type (plist-get (car locs) :type))) ; TODO: Getting the type of the first appearance
(type (plist-get (car locs) :type))) ; INFO: Getting the type of the first appearance
(cond (;; Type
type
(pcase type
Expand All @@ -310,15 +316,20 @@ Get candidate type from DEFS-TABLE, or if not found, from INST-TABLE."
(t ;; Default
nil))))

(cl-defun verilog-ext-capf (&key defs-table inst-table refs-table annotation-fn)
"Complete with identifiers present in DEFS-TABLE, INST-TABLE and REFS-TABLE.
(defun verilog-ext-capf ()
"Complete with identifiers present in various hash tables.
Show annotations using function ANNOTATION-FN.
Tables used: `verilog-ext-tags-defs-table', `verilog-ext-tags-inst-table' and
`verilog-ext-tags-refs-table'.
Verilog-ext `completion-at-point' function to be called by a wrapper function in
the workspace."
Show annotations using function `verilog-ext-capf-annotation-function'."
(interactive)
(let (bounds start end completions)
(let* ((proj (verilog-ext-buffer-proj))
(defs-table (alist-get proj verilog-ext-tags-defs-table nil 'remove #'string=))
(refs-table (alist-get proj verilog-ext-tags-refs-table nil 'remove #'string=))
(inst-table (alist-get proj verilog-ext-tags-inst-table nil 'remove #'string=))
(annotation-fn #'verilog-ext-capf-annotation-function)
bounds start end completions)
(cond (;; Dot completion for object methods/attributes and hierarchical references
(setq bounds (verilog-ext-capf--dot-completion-bounds))
(let (table-entry-value block-type)
Expand Down Expand Up @@ -364,6 +375,12 @@ the workspace."
:annotation-function annotation-fn
:company-docsig #'identity)))

(defun verilog-ext-capf-set (&optional disable)
"Enable or DISABLE builtin capf function."
(if disable
(remove-hook 'completion-at-point-functions #'verilog-ext-capf :local)
(add-hook 'completion-at-point-functions #'verilog-ext-capf nil :local)))


(provide 'verilog-ext-capf)

Expand Down
122 changes: 98 additions & 24 deletions verilog-ext-compile.el
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Original file line number Diff line number Diff line change
Expand Up @@ -38,13 +38,14 @@
;;; Code:

(require 'verilog-mode)
(require 'verilog-ext-template)
(require 'make-mode)


(defgroup verilog-ext-compile nil
"Verilog-ext compilation."
:group 'verilog-ext)

(defconst verilog-ext-compile-filename-re "[a-zA-Z0-9-_\\.\\/]+")

(defconst verilog-ext-compile-msg-code-face 'verilog-ext-compile-msg-code-face)
(defface verilog-ext-compile-msg-code-face
'((t (:inherit font-lock-comment-face)))
Expand All @@ -57,6 +58,62 @@
"Face for compilation binaries."
:group 'verilog-ext-compile)


;;;; Preprocess
(defun verilog-ext-preprocess ()
"Preprocess current file.
Choose among different available programs and update `verilog-preprocessor'
variable."
(interactive)
(let ((tools-available (seq-filter (lambda (bin)
(executable-find bin))
'("verilator" "iverilog" "vppreproc"))))
(pcase (completing-read "Select tool: " tools-available)
;; Verilator
("verilator" (setq verilog-preprocessor "verilator -E __FLAGS__ __FILE__"))
;; Verilog-Perl
("vppreproc" (setq verilog-preprocessor "vppreproc __FLAGS__ __FILE__"))
;; Icarus Verilog: `iverilog' command syntax requires writing to an output file (defaults to a.out).
("iverilog" (let* ((filename-sans-ext (file-name-sans-extension (file-name-nondirectory (buffer-file-name))))
(iver-out-file (concat (temporary-file-directory) filename-sans-ext "_pp_iver.sv")))
(setq verilog-preprocessor (concat "iverilog -E -o" iver-out-file " __FILE__ && "
"echo \"\" && " ; Add blank line between run command and first preprocessed line
"cat " iver-out-file)))))
(verilog-preprocess)
(pop-to-buffer "*Verilog-Preprocessed*")))


;;;; Makefile
(defun verilog-ext-makefile-create ()
"Create Iverilog/Verilator Yasnippet based Makefile.
Create it only if in a project and the Makefile does not already exist."
(interactive)
(let ((project-root (verilog-ext-buffer-proj-root))
file)
(if project-root
(if (file-exists-p (setq file (file-name-concat project-root "Makefile")))
(error "File %s already exists!" file)
(find-file file)
(verilog-ext-template-insert-yasnippet "verilog"))
(error "Not in a project!"))))

(defun verilog-ext-makefile-compile ()
"Prompt to available Makefile targets and compile.
Compiles them with various verilog regexps."
(interactive)
(let ((makefile (file-name-concat (verilog-ext-buffer-proj-root) "Makefile"))
(makefile-need-target-pickup t) ; Force refresh of makefile targets
target cmd)
(unless (file-exists-p makefile)
(error "%s does not exist!" makefile))
(with-temp-buffer
(insert-file-contents makefile)
(makefile-pickup-targets)
(setq target (completing-read "Target: " makefile-target-table)))
(setq cmd (concat "cd " (verilog-ext-buffer-proj-root) " && make " target))
(compile cmd)))


(defmacro verilog-ext-compile-define-mode (name &rest args)
"Macro to define a compilation derived mode for a Verilog error regexp.
Expand Down Expand Up @@ -97,6 +154,8 @@ ARGS is a property list."


;;;; Compilation-re
(defconst verilog-ext-compile-filename-re "[a-zA-Z0-9-_\\.\\/]+")

(defconst verilog-ext-compile-verilator-re
`((verilator-error ,(concat "^%\\(?1:Error: Internal Error\\): \\(?2:" verilog-ext-compile-filename-re "\\):\\(?3:[0-9]+\\):\\(?4:[0-9]+\\)") 2 3 4 2 nil (1 compilation-error-face))
(verilator-error2 ,(concat "^%\\(?1:Error\\): \\(?2:" verilog-ext-compile-filename-re "\\):\\(?3:[0-9]+\\):\\(?4:[0-9]+\\): ") 2 3 4 2 nil (1 compilation-error-face))
Expand Down Expand Up @@ -223,29 +282,44 @@ ARGS is a property list."
:comp-mode verilog-ext-compile-surelog-mode)


;;;; Other compilation commands
(defun verilog-ext-preprocess ()
"Preprocess current file.
Choose among different available programs and update `verilog-preprocessor'
variable."
(interactive)
(let ((tools-available (seq-filter (lambda (bin)
(executable-find bin))
'("verilator" "iverilog" "vppreproc"))))
(pcase (completing-read "Select tool: " tools-available)
;; Verilator
("verilator" (setq verilog-preprocessor "verilator -E __FLAGS__ __FILE__"))
;; Verilog-Perl
("vppreproc" (setq verilog-preprocessor "vppreproc __FLAGS__ __FILE__"))
;; Icarus Verilog: `iverilog' command syntax requires writing to an output file (defaults to a.out).
("iverilog" (let* ((filename-sans-ext (file-name-sans-extension (file-name-nondirectory (buffer-file-name))))
(iver-out-file (concat (temporary-file-directory) filename-sans-ext "_pp_iver.sv")))
(setq verilog-preprocessor (concat "iverilog -E -o" iver-out-file " __FILE__ && "
"echo \"\" && " ; Add blank line between run command and first preprocessed line
"cat " iver-out-file)))))
(verilog-preprocess)
(pop-to-buffer "*Verilog-Preprocessed*")))
(defun verilog-ext-compile ()
"Compile using command of :compile-cmd of `verilog-ext-project-alist' project.
Depending on the command, different syntax highlight will be applied.
The function will detect any of the supported compilation error parsers and will
set the appropriate mode."
(interactive)
(let* ((proj (verilog-ext-buffer-proj))
(compile-cmd (verilog-ext-proj-compile-cmd proj))
(cmd-list (if (not compile-cmd)
(error "You first need to set `:compile-cmd' for current project [%s] in `verilog-ext-project-alist'" proj)
(split-string (verilog-ext-proj-compile-cmd))))
(cmd-args (cdr cmd-list))
(cmd-bin (car cmd-list))
(fn (pcase cmd-bin
("verilator" #'verilog-ext-compile-verilator)
("iverilog" #'verilog-ext-compile-iverilog)
("slang" #'verilog-ext-compile-slang)
("svlint" #'verilog-ext-compile-svlint)
("surelog" #'verilog-ext-compile-surelog)
("verible-verilog-lint" #'verilog-ext-compile-verible)
(_ #'compile)))
(cmd-processed (cond (;; For svlint, make sure the -1 arg is present
(string= cmd-bin "svlint")
(if (member "-1" cmd-args)
compile-cmd
(mapconcat #'identity `(,cmd-bin "-1" ,@cmd-args) " ")))
;; For slang make sure that there is no colored output
((string= cmd-bin "slang")
(if (member "--color-diagnostics=false" cmd-args)
compile-cmd
(mapconcat #'identity `(,cmd-bin "--color-diagnostics=false" ,@cmd-args) " ")))
;; For the rest use the provided command
(t
compile-cmd)))
(cmd (concat "cd " (verilog-ext-buffer-proj-root proj) " && " cmd-processed)))
(funcall fn cmd)))


(provide 'verilog-ext-compile)
Expand Down
2 changes: 1 addition & 1 deletion verilog-ext-font-lock.el
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Original file line number Diff line number Diff line change
Expand Up @@ -271,7 +271,7 @@ obj.method();"
'("begin" "end" "this"))))

;; Once UVM dir has been set, obtained through:
;; (verilog-ext-workspace-typedef-batch-update (verilog-ext-dir-files "/home/user/UVM/src/"))
;; (verilog-ext-typedef-batch-update (verilog-ext-dir-files "/home/user/UVM/src/"))
;; And check value of: `verilog-ext-typedef-align-words'
(defconst verilog-ext-font-lock-uvm-classes
(eval-when-compile
Expand Down
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