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Getting Started Guide
Welcome to the Getting Started Guide!
This guide covers
- System Requirements
- Downloading the code repository
- Installation
- Testing the example project
- Xilinx Vivado 2018.1
- License for Xilinx 10G MAC IP
- Linux OS
- Xilinx VC709
- Xilinx VCU118
- Alpha Data ADM-PCIE-7V3
On your machine, change to the desired directory and execute the following command:
git clone [email protected]:fpgasystems/fpga-network-stack.git
Make sure that Vivado and Vivado HLS are in your PATH. Use version 2018.1
Navigate to the hls directory:
cd hls
Execute the script generate the HLS IP cores for your board:
./generate_hls vc709
For the VCU118 run
./generate_hls vcu118
Navigate to the projects directory:
cd ../projects
Create the example project for your board.
For the Xilinx VC709:
vivado -mode batch -source create_vc709_proj.tcl
For the Alpha DATA ADM-PCIE-7V3:
vivado -mode batch -source reate_adm7v3_proj.tcl
For the Xilinx VCU118:
vivado -mode batch -source create_vcu118_proj.tcl
After the previous command executed, a Vivado project will be created and the Vivado GUI is started.
Click "Generate Bitstream" to generate a bitstream for the FPGA.
Note: The Alpha Data top module is currently not up-to-date.
Deploy the generated .bit file on your board. In case you enabled the iperf module you can use the default linux iperf client to the test the functionality.
Connect the 10G ETH port on another PC to the 10G ETH port on the FPGA board and set the IP address of this PC 10G to be in the same subnet as the FPGA.
From the PC console enter following command to check if you can ping the FPGA successfully by running following command: ping