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* cleanup and new load_netlist function that takes gate library pointer * documentation cleanup * fixed docs * boolean function fixes * fixed the fixes * added use_net_variables parameetr * utils update * use c++17 and activate insertion of braces * fixed standard * fixes * fixed const 1 and 0 nets * create empty plugin * allow to control labeling of global I/O for copied netlists * move resynthesis functions * docu fixes * resynthesis completed * changelog update
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| option(PL_RESYNTHESIS "PL_RESYNTHESIS" OFF) | ||
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| if(PL_RESYNTHESIS OR BUILD_ALL_PLUGINS) | ||
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| file(GLOB_RECURSE RESYNTHESIS_INC ${CMAKE_CURRENT_SOURCE_DIR}/include/*.h) | ||
| file(GLOB_RECURSE RESYNTHESIS_SRC ${CMAKE_CURRENT_SOURCE_DIR}/src/*.cpp) | ||
| file(GLOB_RECURSE RESYNTHESIS_PYTHON_SRC ${CMAKE_CURRENT_SOURCE_DIR}/python/*.cpp) | ||
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| hal_add_plugin(resynthesis | ||
| SHARED | ||
| HEADER ${RESYNTHESIS_INC} | ||
| SOURCES ${RESYNTHESIS_SRC} ${RESYNTHESIS_PYTHON_SRC} | ||
| PYDOC SPHINX_DOC_INDEX_FILE ${CMAKE_CURRENT_SOURCE_DIR}/documentation/resynthesis.rst | ||
| ) | ||
| endif() |
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| Resynthesis | ||
| ========================== | ||
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| .. automodule:: resynthesis | ||
| :members: | ||
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| .. autoclass:: resynthesis.ResynthesisPlugin | ||
| :members: |
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plugins/resynthesis/include/resynthesis/plugin_resynthesis.h
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| // MIT License | ||
| // | ||
| // Copyright (c) 2019 Ruhr University Bochum, Chair for Embedded Security. All Rights reserved. | ||
| // Copyright (c) 2019 Marc Fyrbiak, Sebastian Wallat, Max Hoffmann ("ORIGINAL AUTHORS"). All rights reserved. | ||
| // Copyright (c) 2021 Max Planck Institute for Security and Privacy. All Rights reserved. | ||
| // Copyright (c) 2021 Jörn Langheinrich, Julian Speith, Nils Albartus, René Walendy, Simon Klix ("ORIGINAL AUTHORS"). All Rights reserved. | ||
| // | ||
| // Permission is hereby granted, free of charge, to any person obtaining a copy | ||
| // of this software and associated documentation files (the "Software"), to deal | ||
| // in the Software without restriction, including without limitation the rights | ||
| // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
| // copies of the Software, and to permit persons to whom the Software is | ||
| // furnished to do so, subject to the following conditions: | ||
| // | ||
| // The above copyright notice and this permission notice shall be included in all | ||
| // copies or substantial portions of the Software. | ||
| // | ||
| // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE | ||
| // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
| // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
| // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | ||
| // SOFTWARE. | ||
|
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| /** | ||
| * @file plugin_resynthesis.h | ||
| * @brief This file contains all functions related to the HAL plugin API. | ||
| */ | ||
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| #pragma once | ||
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| #include "hal_core/plugin_system/plugin_interface_base.h" | ||
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| namespace hal | ||
| { | ||
| class Netlist; | ||
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| /** | ||
| * @class ResynthesisPlugin | ||
| * @brief Plugin interface for the netlist resynthesis plugin. | ||
| * | ||
| * This class provides an interface to integrate the netlist resynthesis as a plugin within the HAL framework. | ||
| */ | ||
| class PLUGIN_API ResynthesisPlugin : public BasePluginInterface | ||
| { | ||
| public: | ||
| /** | ||
| * @brief Default constructor for `ResynthesisPlugin`. | ||
| */ | ||
| ResynthesisPlugin() = default; | ||
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| /** | ||
| * @brief Default destructor for `ResynthesisPlugin`. | ||
| */ | ||
| ~ResynthesisPlugin() = default; | ||
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| /** | ||
| * @brief Get the name of the plugin. | ||
| * | ||
| * @returns The name of the plugin. | ||
| */ | ||
| std::string get_name() const override; | ||
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| /** | ||
| * @brief Get the version of the plugin. | ||
| * | ||
| * @returns The version of the plugin. | ||
| */ | ||
| std::string get_version() const override; | ||
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| /** | ||
| * @brief Get a short description of the plugin. | ||
| * | ||
| * @returns The short description of the plugin. | ||
| */ | ||
| std::string get_description() const override; | ||
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| /** | ||
| * @brief Get the plugin dependencies. | ||
| * | ||
| * @returns A set of plugin names that this plugin depends on. | ||
| */ | ||
| std::set<std::string> get_dependencies() const override; | ||
| }; | ||
| } // namespace hal |
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| // MIT License | ||
| // | ||
| // Copyright (c) 2019 Ruhr University Bochum, Chair for Embedded Security. All Rights reserved. | ||
| // Copyright (c) 2019 Marc Fyrbiak, Sebastian Wallat, Max Hoffmann ("ORIGINAL AUTHORS"). All rights reserved. | ||
| // Copyright (c) 2021 Max Planck Institute for Security and Privacy. All Rights reserved. | ||
| // Copyright (c) 2021 Jörn Langheinrich, Julian Speith, Nils Albartus, René Walendy, Simon Klix ("ORIGINAL AUTHORS"). All Rights reserved. | ||
| // | ||
| // Permission is hereby granted, free of charge, to any person obtaining a copy | ||
| // of this software and associated documentation files (the "Software"), to deal | ||
| // in the Software without restriction, including without limitation the rights | ||
| // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
| // copies of the Software, and to permit persons to whom the Software is | ||
| // furnished to do so, subject to the following conditions: | ||
| // | ||
| // The above copyright notice and this permission notice shall be included in all | ||
| // copies or substantial portions of the Software. | ||
| // | ||
| // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE | ||
| // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
| // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
| // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | ||
| // SOFTWARE. | ||
|
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| /** | ||
| * @file resynthesis.h | ||
| * @brief This file contains functions to decompose or re-synthesize combinational parts of a gate-level netlist. | ||
| */ | ||
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| #pragma once | ||
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| #include "hal_core/defines.h" | ||
| #include "hal_core/utilities/result.h" | ||
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| namespace hal | ||
| { | ||
| class Netlist; | ||
| class Gate; | ||
| class GateType; | ||
| class GateLibrary; | ||
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| namespace resynthesis | ||
| { | ||
| /** | ||
| * Decompose a combinational gate into a small circuit of AND, OR, XOR, and INVERT gates. | ||
| * For each output pin, the resolved Boolean function (only dependent on input pins) is determined. | ||
| * All these Boolean functions are then converted into a netlist using the previously mentioned primitive gates. | ||
| * The target gate is then replaced in the original netlist with the circuit that was just generated. | ||
| * The target gate is only deleted if `delete_gate` is set to `true`. | ||
| * Gate replacement will fail if the gate library of the netlist does not contain suitable AND, OR, XOR, and INVERT gate types. | ||
| * | ||
| * @param[in] nl - The netlist to operate on. | ||
| * @param[in] gate - The gate to decompose. | ||
| * @param[in] delete_gate - Set `true` to delete the original gate, `false` to keep it in the netlist. Defaults to `true`. | ||
| * @return OK() on success, an error otherwise. | ||
| */ | ||
| Result<std::monostate> decompose_gate(Netlist* nl, Gate* gate, const bool delete_gate = true); | ||
|
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| /** | ||
| * Decompose all combinational gates of the specified types into small circuits of AND, OR, XOR, and INVERT gates. | ||
| * For all output pins of each gate, the resolved Boolean function (only dependent on input pins) is determined. | ||
| * All these Boolean functions are then converted into a circuit using the previously mentioned primitive gates. | ||
| * The target gates are then replaced (and thereby deleted) in the original netlist with the circuit that was just generated. | ||
| * Gate replacement will fail if the gate library of the netlist does not contain suitable AND, OR, XOR, and INVERT gate types. | ||
| * | ||
| * @param[in] nl - The netlist to operate on. | ||
| * @param[in] gate_types - The gate types to be decomposed. | ||
| * @return OK() and the number of decomposed gates on success, an error otherwise. | ||
| */ | ||
| Result<u32> decompose_gates_of_type(Netlist* nl, const std::vector<const GateType*>& gate_types); | ||
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| /** | ||
| * Re-synthesize a combinational gate by calling Yosys on a functional description of the gate using a reduced gate library. | ||
| * For each output pin, the resolved Boolean function (only dependent on input pins) is determined. | ||
| * All these Boolean functions are then written to an HDL file that is functionally equivalent to the target gate. | ||
| * This file is fed to Yosys and subsequently synthesized to a netlist again by using the provided gate library. | ||
| * The provided gate library should be a subset of the gate library that was used to parse the netlist. | ||
| * The target gate is then replaced in the original netlist with the circuit that was just generated. | ||
| * The target gate is only deleted if `delete_gate` is set to `true`. | ||
| * | ||
| * @param[in] nl - The netlist to operate on. | ||
| * @param[in] gate - The gate to re-synthesize. | ||
| * @param[in] target_gl - The gate library that is a subset of the gate library used to parse the netlist. | ||
| * @param[in] delete_gate - Set `true` to delete the original gate, `false` to keep it in the netlist. Defaults to `true`. | ||
| * @return OK() on success, an error otherwise. | ||
| */ | ||
| Result<std::monostate> resynthesize_gate(Netlist* nl, Gate* gate, GateLibrary* target_gl, const bool delete_gate = true); | ||
|
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| /** | ||
| * Re-synthesize all specified combinational gates by calling Yosys on a functional description of the gates using a reduced gate library. | ||
| * For all output pins of each gate, the resolved Boolean function (only dependent on input pins) is determined. | ||
| * All Boolean functions of a gate are then written to an HDL file that is functionally equivalent to the gate. | ||
| * These files are fed to Yosys and subsequently synthesized to a netlist again by using the provided gate library. | ||
| * The provided gate library should be a subset of the gate library that was used to parse the netlist. | ||
| * The gates are then replaced in the original netlist with the circuits that were just generated. | ||
| * This process is repeated for every gate, hence they are re-synthesized in isolation. | ||
| * | ||
| * @param[in] nl - The netlist to operate on. | ||
| * @param[in] gates - The gates to re-synthesize. | ||
| * @param[in] target_gl - The gate library that is a subset of the gate library used to parse the netlist. | ||
| * @return OK() and the number of re-synthesized gates on success, an error otherwise. | ||
| */ | ||
| Result<u32> resynthesize_gates(Netlist* nl, const std::vector<Gate*>& gates, GateLibrary* target_gl); | ||
|
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| /** | ||
| * Re-synthesize all combinational gates of the specified types by calling Yosys on a functional description of the gates using a reduced gate library. | ||
| * For all output pins of each gate, the resolved Boolean function (only dependent on input pins) is determined. | ||
| * All Boolean functions of a gate are then written to an HDL file that is functionally equivalent to the gate. | ||
| * These files are fed to Yosys and subsequently synthesized to a netlist again by using the provided gate library. | ||
| * The provided gate library should be a subset of the gate library that was used to parse the netlist. | ||
| * The gates are then replaced in the original netlist with the circuits that were just generated. | ||
| * This process is repeated for every gate, hence they are re-synthesized in isolation. | ||
| * | ||
| * @param[in] nl - The netlist to operate on. | ||
| * @param[in] gate_types - The gate types to be re-synthesized. | ||
| * @param[in] target_gl - The gate library that is a subset of the gate library used to parse the netlist. | ||
| * @return OK() and the number of re-synthesized gates on success, an error otherwise. | ||
| */ | ||
| Result<u32> resynthesize_gates_of_type(Netlist* nl, const std::vector<const GateType*>& gate_types, GateLibrary* target_gl); | ||
|
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| // TODO update docs below | ||
|
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| /** | ||
| * Re-synthesize the combinational gates of the subgraph by calling Yosys on a Verilog netlist representation of the subgraph using a reduced gate library. | ||
| * All gates of the subgraph are written to a Verilog netlist file which is then fed to Yosys and subsequently synthesized to a netlist again by using the provided gate library. | ||
| * The provided gate library should be a subset of the gate library that was used to parse the netlist. | ||
| * The gates are then replaced in the original netlist with the circuit that was just generated. | ||
| * | ||
| * @param[in] nl - The netlist to operate on. | ||
| * @param[in] subgraph - The subgraph to re-synthesize. | ||
| * @param[in] target_gl - The gate library that is a subset of the gate library used to parse the netlist. | ||
| * @return OK() and the number of re-synthesized gates on success, an error otherwise. | ||
| */ | ||
| Result<u32> resynthesize_subgraph(Netlist* nl, const std::vector<Gate*>& subgraph, GateLibrary* target_gl); | ||
|
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| /** | ||
| * Re-synthesize the combinational gates of the specified types as a subgraph by calling Yosys on a Verilog netlist representation of the subgraph induced by these gates using a reduced gate library. | ||
| * All gates of the subgraph are written to a Verilog netlist file which is then fed to Yosys and subsequently synthesized to a netlist again by using the provided gate library. | ||
| * The provided gate library should be a subset of the gate library that was used to parse the netlist. | ||
| * The gates are then replaced in the original netlist with the circuit that was just generated. | ||
| * | ||
| * @param[in] nl - The netlist to operate on. | ||
| * @param[in] gate_types - The gate types to be re-synthesized. | ||
| * @param[in] target_gl - The gate library that is a subset of the gate library used to parse the netlist. | ||
| * @return OK() and the number of re-synthesized gates on success, an error otherwise. | ||
| */ | ||
| Result<u32> resynthesize_subgraph_of_type(Netlist* nl, const std::vector<const GateType*>& gate_types, GateLibrary* target_gl); | ||
| } // namespace resynthesis | ||
| } // namespace hal |
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