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Merge pull request #158 from embeddedTS/linux-upstream-v5.10.231
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@@ -131,6 +131,17 @@ Description: | |
will be present in sysfs. Writing 1 to this file | ||
will perform reset. | ||
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What: /sys/bus/pci/devices/.../reset_subordinate | ||
Date: October 2024 | ||
Contact: [email protected] | ||
Description: | ||
This is visible only for bridge devices. If you want to reset | ||
all devices attached through the subordinate bus of a specific | ||
bridge device, writing 1 to this will try to do it. This will | ||
affect all devices attached to the system through this bridge | ||
similiar to writing 1 to their individual "reset" file, so use | ||
with caution. | ||
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What: /sys/bus/pci/devices/.../vpd | ||
Date: February 2008 | ||
Contact: Ben Hutchings <[email protected]> | ||
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Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Binding for Analog Devices AXI clkgen pcore clock generator | ||
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maintainers: | ||
- Lars-Peter Clausen <[email protected]> | ||
- Michael Hennerich <[email protected]> | ||
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description: | | ||
The axi_clkgen IP core is a software programmable clock generator, | ||
that can be synthesized on various FPGA platforms. | ||
Link: https://wiki.analog.com/resources/fpga/docs/axi_clkgen | ||
properties: | ||
compatible: | ||
enum: | ||
- adi,axi-clkgen-2.00.a | ||
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clocks: | ||
description: | ||
Specifies the reference clock(s) from which the output frequency is | ||
derived. This must either reference one clock if only the first clock | ||
input is connected or two if both clock inputs are connected. The last | ||
clock is the AXI bus clock that needs to be enabled so we can access the | ||
core registers. | ||
minItems: 2 | ||
maxItems: 3 | ||
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clock-names: | ||
oneOf: | ||
- items: | ||
- const: clkin1 | ||
- const: s_axi_aclk | ||
- items: | ||
- const: clkin1 | ||
- const: clkin2 | ||
- const: s_axi_aclk | ||
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'#clock-cells': | ||
const: 0 | ||
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reg: | ||
maxItems: 1 | ||
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required: | ||
- compatible | ||
- reg | ||
- clocks | ||
- clock-names | ||
- '#clock-cells' | ||
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additionalProperties: false | ||
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examples: | ||
- | | ||
clock-controller@ff000000 { | ||
compatible = "adi,axi-clkgen-2.00.a"; | ||
#clock-cells = <0>; | ||
reg = <0xff000000 0x1000>; | ||
clocks = <&osc 1>, <&clkc 15>; | ||
clock-names = "clkin1", "s_axi_aclk"; | ||
}; |
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