Skip to content

Home

Jump to bottom
getvictor edited this page Aug 12, 2013 · 33 revisions

Quick Start
FAQ

Features

EDA Playground gives engineers immediate hands-on exposure to simulating Verilog/SystemVerilog/VHDL. All you need is a web browser. The goal is to accelerate learning of design/testbench development with easier code sharing, and with simpler access to simulators and libraries.

  • With a simple click, run your code and see console output in real time. Pick another simulator version and run it again.
  • Save and share your code snippets with others by sending them a link. Perfect for web forum discussions or emails. Great for asking questions: Why am I seeing this result?, or sharing your knowledge: This is how I would do it.
  • Quickly try something out
    • Try out some new SystemVerilog syntax before using it on your project. For example, Does this simulator version support IEEE 1800-2012 syntax?
    • Try out a library that you're thinking of using without installing it. Does it do what you expect?
    • Modify your friend's shared code and run it.
  • Browse and use a large repository of working code examples and templates.

Playground

Real Usage Examples

  • EDA Playground was used during technical interviews to test candidates' Verilog coding skills at a major semiconductor company.
  • I work in a large environment where compiles and sims take a considerable amount of time. When I'm developing/debugging, sometimes I want to use Verilog/SystemVerilog syntax that I have not used before. (Examples: wild equality, binding to the same port multiple times.) I don't want to stick my code into the environment and hope that the simulator supports it, and that the feature works as I expect it to. Instead, I first do a quick prototype on EDA Playground. -Design Verification Engineer at AMD
  • A student was working on a project and ran into an issue that he needed help with. He saved the relevant code on EDA Playground and posted the question on Stack Overflow with a link to his code. Another person made modifications to the student's code and posted the new link in the reply.
  • The chip design team saw a simulator failure/crash when certain Verilog syntax was used. The observer saved the example on EDA Playground and sent it to the simulator support team. The issue was 100% reproducible, which sped up time-to-patch.
  • An engineer hit a compile issue, and the simulator spit out a confusing message. She put the relevant code on EDA Playground and tried different simulators and other versions of the same simulator. Another simulator gave a clearer message (it accepted the syntax, but gave a warning), and the engineer quickly fixed her code.

Simulators

The following simulators can be used.

On public EDA Playground -- The FREE Verilog IDE:

On private EDA Playground:

  • All simulators available on public version.
  • Any additional simulators that your company/university has developed or has licenses for.

Feature Requests and Bug Fixes

Request new features and bug fixes here: https://github.com/getvictor/eda-playground/issues
Or Tweet to @EDAPlayground

Credits

EDA Playground was created in May 2013 by Victor Lyuboslavsky.
EDA Playground on Twitter
Victor EDA on LinkedIn

Clone this wiki locally